CH7009A Datasheet, PDF (1/46 Pages) List of Unclassifed Manufacturers – Chrontel CH7009 DVI / TV Output Device

CH7009A
CHRONTEL
Chrontel CH7009 DVI / TV Output Device
Features
• DVI Transmitter up to 165MHz
• DVI low jitter PLL
• DVI hot plug detection
• TV output supporting up to 1024x768 graphics
resolutions
• Macrovision^TM 7.X copy protection support
• Programmable digital interface supports RGB and
YCrCb
• TrueScale^TM rendering engine supports underscan in all
TV output resolutions
• Enhanced text sharpness and adaptive flicker removal
with up to 7 lines of filtering
• Support for all NTSC and PAL formats
• Provides CVBS, S-Video and SCART (RGB) outputs
• TV connection detect
• Programmable power management
• 10-bit video DAC outputs
• Fully programmable through I²C port
• Complete Windows and DOS driver support
• Low voltage interface support to graphics device
• Offered in a 64-pin LQFP package
General Description
The CH7009 is a Display controller device which accepts a
digital graphics input signal, and encodes and transmits
data through a DVI TMDS^TM link (DFP can also be
supported) or TV output (analog composite, s-video or
RGB). The device accepts data over one 12-bit wide
variable voltage data port which supports five different
data formats including RGB and YCrCb.
The DVI processor includes a low jitter PLL for generation
of the high frequency serialize clock, and all circuitry
required to encode, serialize and transmit data. The
CH7009 comes in versions able to drive a DVI display at a
pixel rate of up to 165MHz, supporting UXGA resolution
displays. No scaling of input data is performed on the data
output to the DVI device.
The TV-Out processor will perform non-interlace to
interlace conversion with scaling and flicker filters, and
encode the data into any of the NTSC or PAL video
standards. The scaling and flicker filter is adaptive and
programmable to enable superior text display. Eight
graphics resolutions are supported up to 1024 by 768 with
full vertical and horizontal underscan capability in all
modes. A high accuracy low jitter phase locked loop is
integrated to create outstanding video quality. Support is
provided for Macrovision^TM and RGB bypass mode which
enables driving a VGA CRT with the input data.
XCLK,XCLK* ₂
Clock
Driver
D[11:0] ₁₂
Data
Latch,
24
Demux
H,V,DE ₃
H,V,DE
VREF
Latch
3
XI/FIN,XO
2
P-OUT / TLDET*
BCO
DVI (TMDS ^TM link) PLL
2
DVI
DVI
DVI
2
24
Encode
Serialize
Driver
2
3
2
2
IIC
Control
PLL3
Timing
Scaling
3 _{Scan Conv}
24
Flicker Filt
TV
Encode
Four
10-bit
DAC's
24
Figure 1: Functional Block Diagram
201-0000-035 Rev 1.1, 5/8/2000 *TMDS is Trademark of Silicon Image Inc.
TLC,TLC*
TDC0,TDC0*
TDC1,TDC1*
TDC2,TDC2*
VSWING
HPDET
GPIO[1:0]
AS
SC
SD
RESET*
C/H SYNC
ISET
CVBS (DAC3)
Y (DAC 1)
C (DAC 2)
CVBS (DAC0)
1