AMC8500 Datasheet, PDF (22/27 Pages) List of Unclassifed Manufacturers – TWO PHASE VARIABLE SPEED FAN MOTOR CONTROLLER

Preliminary Specification
aMC8500
Figure 38- Balanced Technology Extended (BTX) Closed Loop Speed Control
12 V
Duty Cycle
to Voltage
Converter
Control
Signal ¹⁰
Input
k
10 k
6.8 k
74AC86PC
H
Temperature
Controlled
Clamp
T
H
2.8 k
20 k
47 k
6.8 k
Thermistor
(°C) (Ω)
24 10464
25 10061
26 9712
28 9027
30 8394
32 7828
34 7291
36 6799
β = 3300
100 nF
5
330 nF
7
22 μF
8
330 nF
9
1M 6
Reference
Ref
Op Amp
FB
Error
SC
Oscillator
10
12
3
4
Under Voltage
Lockout
Hall Amplifier
Non-Overlap
Commutation
Fault Timer
Power Down
Kick Start
Min Speed
Comp
PWM Comp
PWM
Logic
Digital
Detector
H
SN
M
NS
16
Motor
Drives
Thermal
Shutdown
Current
Limit
Latch
R
Q
S
10 μA
Current Limit
Comp
11
14
Frequency to Voltage Converter _{10 k}
100 k
10 nF 150 k
1
V_DD
10 k
FGRL
Out
15
13
2
10 nF
Figure 39- Fan Speed versus Control Signal Duty Cycle
for Various Inlet Air Temperatures
4800
Inlet Air Temperature °C
36
4000
34
32
3200
30
28
2400
26
Min Speed Set
1600 Intercept Points
24
20%
800 _10%
2600
2200
Figure 40- Fan Speed versus Motor Voltage
for Various Control Signal Duty Cycles
Control Signal = 0 to 5.0 V, 10 kHz
Inlet Air Temperature = 30°C
70% Duty Cycle
1800
50% Duty Cycle
1400
1000
30% Duty Cycle
0
0
20
40
60
80
100
Control Signal Duty Cycle (%)
600
10.8 11.2 11.6 12.0 12.4 12.8 13.2 13.6
Motor Voltage (V)
The above circuit controls fan speed in a closed loop manner that is proportional to the control signal duty cycle and inlet air
temperature. A voltage indicating the required fan speed or Reference is applied to Pin 7 and is derived from the Duty Cycle to Voltage
Converter and Temperature Controlled Clamp circuits. The Duty Cycle to Voltage Converter consists of an XOR gate buffer that drives a
10 k, 22 μF low pass filter, with the high state level limited by the Temperature Controlled Clamp. A voltage indicating the actual fan
speed or Feedback is applied to Pin 8 and is derived from the Frequency to Voltage Converter that consists of two XOR gates. The first
XOR buffers the FGRL tachometer signal and connects to the second which is configured as an edge transition one-shot that drives a
100 k, 330 nF low pass filter. The Op Amp compares the difference between the Reference and Feedback voltages and generates an
Error signal that drives Pin 6 in a corrective fashion causing the fan to run either faster or slower so that the Feedback voltage level
becomes the same as the Reference. Performance data is shown in the above graphs. Note that the Error signal is applied to Pin 6
instead of Pin 10 and that Pin 10 must be biased between 1.0 V to 3.0 V for proper operation.
© Andigilog, Inc. 2006
- 22 -
www.andigilog.com
August 2006 - 70A04018