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OX12PCI840 Datasheet, PDF (21/32 Pages) List of Unclassifed Manufacturers – Integrated Parallel Port and PCI interface | |||
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OXFORD SEMICONDUCTOR LTD.
5.3.10 Configuration B register
ECR[7:5] must be set to â111â to access this register. Read
only, all bits will be set to 0, except for bit[6] which will
reflect the state of the interrupt.
5.3.11 Extended control register âECRâ
The Extended control register is located at offset 002h in
upper block. It is used to configure the operation of the
parallel port.
ECR[4:0]: Reserved - write
These bits are reserved and must always be set to
â00001â.
ECR[0]: Empty - read
When DCR[5} = â0â
logic 0 â FIFO contains at least one byte
logic 1 â FIFO completely empty
When DCR[5} = â1â
logic 0 â FIFO contains at least one byte
logic 1 â FIFO contains less than one byte
ECR[1]: Full - read
When DCR[5} = â0â
OX12PCI840
logic 0 â FIFO has at least one free byte
FIFO completely full
When DCR[5} = â1â
logic 0 â FIFO has at least one free byte
logic 1 â FIFO full
ECR[2]: serviceIntr - read
When DCR[5} = â0â
logic 1 â writeIntrThreshold (8) free bytes or more in
FIFO
When DCR[5} = â1â
logic 1 â readIntrThreshold (8) bytes or more in FIFO
ECR[7:5]: Mode â read / write
These bits define the operational mode of the parallel port.
logic â000â
SPP
logic â001â
logic â010â
PS2
Reserved
logic â011â
ECR
logic â100â
EPP
logic â101â
Reserved
logic â110â
Test
logic â111â
Config
Data Sheet Revision 1.2
Page 21
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