OX12PCI840 Datasheet, PDF (19/32 Pages) List of Unclassifed Manufacturers – Integrated Parallel Port and PCI interface

OXFORD SEMICONDUCTOR LTD.
OX12PCI840
5.3 Register Description
The parallel port registers are described below. (NB it is assumed that the upper block is placed 400h above the lower block).
Register Address R/W Bit 7
Bit 6 Bit 5
Bit 4
Name
Offset
Bit 3 Bit 2
Bit 1
SPP (Compatibility Mode) Registers
PDR
000h R/W
Parallel Port Data Register
ecpAFifo
000h R/W
ECP FIFO : Address / RLE
DSR
001h
R nBUSY ACK#
PE
SLCT ERR# INT#
1
(EPP mode)
Bit 0
Timeout
(Other modes)
001h
DCR
002h
EPPA ¹
003h
EPPD1 ¹
004h
EPPD2 ¹
005h
EPPD3 ¹
006h
EPPD4 ¹
007h
EcpDFifo
400h
TFifo
400h
CnfgA
400h
CnfgB
401h
ECR
402h
-
403h
R nBUSY ACK#
R/W
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
R
0
int
R/W
Mode[2:0]
-
PE
SLCT ERR# INT#
DIR INT_EN nSLIN# INIT#
EPP Address Register
EPP Data 1 Register
EPP Data 2 Register
EPP Data 3 Register
EPP Data 4 Register
ECP Data FIFO
Test FIFO
Configuration A Register – always 90h
‘000000’
Must write ‘00001’
Reserved
Table 6: Parallel port register set
1
1
nAFD# nSTB#
Note 1: These registers are only available in EPP mode.
Note 2 : Prefix ‘n’ denotes that a signal is inverted at the connector. Suffix ‘#’ denotes active-low signalling
The reset state of PDR, EPPA and EPPD1-4 is not determinable (i.e. 0xXX). The reset value of DSR is ‘XXXXX111’. DCR and
ECR are reset to ‘0000XXXX’ and ‘00000001’ respectively.
5.3.1 Parallel port data register ‘PDR’
PDR is located at offset 000h in the lower block. It is the
standard parallel port data register. Writing to this register
in mode 000 will drive data onto the parallel port data lines.
In all other modes the drivers may be tri-stated by setting
the direction bit in the DCR. Reads from this register return
the value on the data lines.
5.3.2 ECP FIFO Address / RLE
A data byte written to this address will be interpreted as an
address if bit(7) is set, otherwise an RLE count for the next
data byte. Count = bit(6:0) + 1.
5.3.3 Device status register ‘DSR’
DSR is located at offset 001h in the lower block. It is a read
only register showing the current state of control signals
from the peripheral. Additionally in EPP mode, bit 0 is set
to ‘1’ when an operation times out (see section 5.1.3)
DSR[0]:
EPP mode: Timeout
logic 0 ⇒Timeout has not occurred.
logic 1 ⇒Timeout has occurred (Reading this bit clears it).
Other modes: Unused
This bit is permanently set to 1.
DSR[1]: Unused
This bit is permanently set to 1.
Data Sheet Revision 1.2
Page 19