NRF2401 Datasheet, PDF (20/37 Pages) List of Unclassifed Manufacturers – Single chip 2.4 GHz Transceiver

PRODUCT SPECIFICATION
Q5) 6LQJOH &KLS  *+] 5DGLR 7UDQVFHLYHU
$''5[
$''5
103 102 101 ….
71
70
69
68
67
66
65 64
ADDR1
63 62 61 …. 31 30 29 28 27 26 25 24
Table 12 Address of receiver #2 and receiver #1.
Bit 103 – 64:
ADDR2: Receiver address channel 2, up to 40 bit.
Bit 63 – 24: ADDR1
ADDR1: Receiver address channel 1, up to 40 bit.
NOTE!
Bits in ADDRx exceeding the address width set in ADDR_W are redundant
and can be set to logic 0.
$''5B: &5&
$''5B:
&5&B/ &5&B(1
23
22
21
20
19
18
17
16
Table 13 Number of bits reserved for RX address + CRC setting.
Bit 23 – 18:
ADDR_W: Number of bits reserved for RX address in ShockBurst™
packages.
NOTE:
Maximum number of address bits is 40 (5 bytes). Values over 40 in
ADDR_W are not valid.
Bit 17:
CRC_L:
CRC length to be calculated by nRF2401 in ShockBurst™.
Logic 0: 8 bit CRC
Logic 1: 16 bit CRC
Bit: 16:
CRC_EN:
Enables on-chip CRC generation (TX) and verification (RX).
Logic 0: On-chip CRC generation/checking disabled
Logic 1: On-chip CRC generation/checking enabled
NOTE:
An 8 bit CRC will increase the number of payload bits possible in each
ShockBurst™ data packet, but will also reduce the system integrity.
Nordic VLSI ASA - Vestre Rosten 81, N-7075 Tiller, Norway - Phone [phone] - Fax [phone]
Revision: 1.0
Page 20 of 37
March 2003