NRF2401 Datasheet, PDF (12/37 Pages) List of Unclassifed Manufacturers – Single chip 2.4 GHz Transceiver

PRODUCT SPECIFICATION
Q5) 6LQJOH &KLS  *+] 5DGLR 7UDQVFHLYHU
Q5) 6KRFN%XUVWΠ5HFHLYH
MCU interface pins: CE, DR1, CLK1 and DATA (one RX channel receive)
1. Correct address and size of payload of incoming RF packages are set when
nRF2401 is configured to ShockBurst™ RX.
2. To activate RX, set CE high.
3. After 200 µs settling, nRF2401 is monitoring the air for incoming
communication.
4. When a valid package has been received (correct address and CRC found),
nRF2401 removes the preamble, address and CRC bits.
5. nRF2401 then notifies (interrupts) the MCU by setting the DR1 pin high.
6. MCU may (or may not) set the CE low to disable the RF front end (low
current mode).
7. The MCU will clock out just the payload data at a suitable rate (ex. 10
kbps).
8. When all payload data is retrieved nRF2401 sets DR1 low again, and is
ready for new incoming data package if CE is kept high during data
download. If the CE was set low, a new start up sequence can begin, see
Figure 16.
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In direct mode the nRF2401 works like a traditional RF device. Data must be at
1Mbps, or 250kbps at low data rate setting, for the receiver to detect the signals.
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MCU interface pins: CE, DATA
1. When application MCU has data to send, set CE high
2. The nRF2401 RF front end is now immediately activated, and after 200 µs
settling time, data will modulate the carrier directly.
3. All RF protocol parts must hence be implemented in MCU firmware
(preamble, address and CRC).
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MCU interface pins: CE, CLK1, and DATA
1. Once the nRF2401 is configured and powered up (CE high) in direct RX
mode, DATA will start to toggle due to noise present on the air.
2. CLK1 will also start to toggle as nRF2401 is trying to lock on to the
incoming data stream.
3. Once a valid preamble arrives, CLK1 and DATA will lock on to the
incoming signal and the RF package will appear at the DATA pin with the
same speed as it is transmitted.
4. To enable the demodulator to re-generate the clock, the preamble must be
8 bits toggling hi-low, starting with low if the first data bit low.
5. In this mode no data ready (DR) signals is available. Address and
checksum verification must also be done in the receiving MC.
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Revision: 1.0
Page 12 of 37
March 2003