VS1011 Datasheet, PDF (19/43 Pages) List of Unclassifed Manufacturers – MP3 AUDIO CODEC

VLSI
Solution ^y
VS1011 PRELIMINARY
VS1011
7. SPI BUSES
XCS
SCK
SI
SO
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
30 31
3210
000000110000
don’t care
don’t care
instruction (read)
0000000000
address
data out
15 14
000000
10
X
XCS
SCK
SI
SO
Figure 5: SCI Word Read
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
30 31
3 2 1 0 15 14
000000100000
10
X
instruction (write)
address
data out
0000000000000000 00
0 0X
7.5 SPI Timing Diagram
Figure 6: SCI Word Write
Symbol Min
Max Unit
tXCSS
5
ns
tSU
-26
ns
tH
2
XTALI cycles
tZ
0
ns
tWL
2
XTALI cycles
tWH
2
XTALI cycles
tV
2 (+ 25ns¹) XTALI cycles
tXCSH -26
ns
tXCS
2
XTALI cycles
tDIS
10 ns
1 _{25ns is when pin loaded with 100pF capacitance. The time is shorter with lower capacitance.}
Note: As tWL and tWH, as well as tH require at least 2 clock cycles, the maximum speed for the SPI
bus that can easily be used is 1/6 of VS1011’s external clock speed XTALI. Slightly higher speed can be
achieved with very careful timing tuning. For details, see Application Notes for VS10XX.
Note: Negative numbers mean that the signal can change in different order from what is shown in the
diagram.
Version 0.71, 2004-07-20
19