VS1011 Datasheet, PDF (17/43 Pages) List of Unclassifed Manufacturers – MP3 AUDIO CODEC

VLSI
Solution ^y
VS1011 PRELIMINARY
VS1011
7. SPI BUSES
7.3 Serial Protocol for Serial Data Interface (SDI)
7.3.1 General
The serial data interface operates in slave mode so the DCLK signal must be generated by an external
circuit.
Data (SDATA signal) can be clocked in at either the rising or falling edge of DCLK (Chapter 8.6).
VS1011 assumes its data input to be byte-sychronized. SDI bytes may be transmitted either MSb or LSb
first, depending of contents of SCI MODE (Chapter 8.6).
7.3.2 SDI in VS1002 Native Modes (New Mode)
In VS1002 native modes (which are available also in VS1011), byte synchronization is achieved by
XDCS (or XCS if SM SDISHARE is 1). The state of XDCS (or XCS) may not change while a data
byte transfer is in progress. To always maintain data synchronization even if there may be glitches in the
boards using VS1011, it is recommended to turn XDCS (or XCS) every now and then, for instance once
after every flash data block or a few kilobytes, just to keep sure the host and VS1011 are in sync.
For new designs, using VS1002 native modes are recommended, as they are easier to implement than
BSYNC generation.
7.3.3 SDI in VS1001 Compatibility Mode
BSYNC
SDATA
DCLK
D7
D6
D5
D4
D3
D2
D1
D0
Figure 4: BSYNC Signal.
When VS1011b is running in VS1001 compatibility mode, a BSYNC signal must be generated to ensure
correct byte-alignment of the input bitstream. The first DCLK sampling edge (rising or falling, depending
on selected polarity), during which the BSYNC is high, marks the first bit of a byte (LSB if LSB-first
order is used, MSB if MSB-first order is used).
7.3.4 SDI and DREQ
The DREQ signal of the data interface is used in slave mode to signal if VS1011’s FIFO is capable of
receiving more input data. If DREQ is high, VS1011 can take at least 32 bytes of data. When there is
less than 32 bytes of free space, DREQ is turned low, and the sender should stop transferring new data.
Version 0.71, 2004-07-20
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