AC104QF Datasheet, PDF (19/37 Pages) List of Unclassifed Manufacturers – Ultra Low Power 10/100 Quad RMII Ethernet Transceiver

AC104QF
Ultra Low Power 10/100 Quad RMII Ethernet Transceiver
Register 0: Control Register
Reg.bit
Name
0.15 Reset
0.14 Loopback
0.13 Speed Select
Description
1 = PHY reset.
This bit is self-clearing.
1 = Enable loopback mode. This will loopback TXD to RXD and
ignore all the activity on the cable media.
0 = Normal operation.
1 = 100Mbps 0 = 10Mbps.
0.12 ANeg Enable 1 = Enable Auto-Negotiate process (overrides 0.13 and 0.8)
0 = Disable Auto-Negotiate process. Mode selection is
controlled via bit 0.8, 0.13 or through mode pin.
0.11 Power Down 1 = Power down. All blocks except for SMI will be turned off.
Setting PWRDN pin to high will achieve the same result.
0 = Normal operation.
0.10 Isolate
1 = N/A
0 = Normal operation.
0.9 Restart ANeg 1 = Restart Auto-Negotiation process.
0 = Normal operation.
0.8 Duplex Mode 1 = Full duplex.
0 = Half duplex.
0.7
0.[6:0]
Collision Test
Reserved
1 = Enable collision test, which issues the COL signal in
response to the assertion of TX_EN signal. Collision test is
disabled if PCSBP pin is high. Collision test is enabled regardless
of the duplex mode.
0 = Disable COL test.
* Refer to Mode Table
Mode
RW/SC
RW
Default
0
0
RW * See Note
RW * See Note
RW
0
R
0
RW/SC
0
RW * See Note
RW
0
RW
0000000
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