AC104QF Datasheet, PDF (18/37 Pages) List of Unclassifed Manufacturers – Ultra Low Power 10/100 Quad RMII Ethernet Transceiver

AC104QF
Ultra Low Power 10/100 Quad RMII Ethernet Transceiver
REGISTER DESCRIPTIONS
The first seven registers of the MII register set are
defined by the MII specification. In addition to these
required registers are several Altima
Communications Inc. specific registers. There are
reserved registers and/or bits that are for Altima
internal use only. The following standard registers
are supported. (Register numbers are in Decimal
format, the values are in Hex format):
NOTE: When writing to registers it is recommended
that a read/modify/write operation be performed, as
unintended bits may get set to unwanted states. This
applies to all registers, including those with reserved
bits.
REGISTERS 1-7
Register
0
1
2
3
4
5
6
7
Description
Control Register
Status Register
PHY Identifier 1 Register
PHY Identifier 2 Register
Auto-Negotiation Advertisement Register
Auto-Negotiation Link Partner Ability Register
Auto-Negotiation Expansion Register
Next Page Advertisement Register
REGISTERS 8-31
Register
8-15
16
17
18
19
20
21
22
23
24
25-31
Description
Reserved
Polarity and Interrupt Level Register
Interrupt Control/Status Register
Diagnostic Register
Power/Loopback Register
Cable Measurement Register
Receive Error Counter Register
Reserved
Reserved
Mode Control Register
Reserved
Default
3000
7849
0022
5541
01E1
0001
0004
2001
Default
XXXX
03C0
0000
5020
8060
XXXX
0304
XXXX
0000
0000
XXXX
LEGEND:
RW
SC
LL
RO
RC
LH
Read and Write Access
Self Clearing
Latch Low until cleared by reading
Read Only
Cleared on Read
Latch High until Cleared by reading
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Altima Communications Inc. reserves the right to make changes to this document without notice.
Document Revision 4.0
Page 18 of 37