AC104QF Datasheet, PDF (12/37 Pages) List of Unclassifed Manufacturers – Ultra Low Power 10/100 Quad RMII Ethernet Transceiver

AC104QF
Ultra Low Power 10/100 Quad RMII Ethernet Transceiver
code-groups that follow the negation of the TX_EN
signal. The encapsulated data stream is converted
from 4-bit nibbles to 5-bit code-groups. During the
inter-packet gap, when there is no data present, a
continuous stream of IDLE code-groups are
transmitted. When TX_ER is asserted while TX_EN
is active, the Transmit Error code-group /H/ is substi-
tuted for the translated 5B code word. The 4B/5B
encoding is bypassed when Reg. 21.1 is set to “1”, or
the PCSBP pin is strapped high.
In 100Base-TX mode, the 5-bit transmit data stream
is scrambled as defined by the TP-PMD Stream
Cipher function in order to reduce radiated emissions
on the twis ted pair cable. The scrambler encodes a
plain text NRZ bit stream using a key stream periodic
sequence of 2047 bits generated by the recursive
linear function:
X[n] = X[n-11] + X[n-9] (modulo 2)
The scrambler reduces peak emissions by randomly
spreading the signal energy over the transmitted fre-
quency range, thus eliminating peaks at any single
frequency. For repeater applications, where all ports
transmit the same data simultaneously, signal energy
is spread further by using a non-repeating sequence
for each Phy, i.e., the scrambled seed is unique for
each different Phy based on the Phy address.
for the MLT-3 data. Asserting FX_SEL high will
disable this encoding.
The slew rate of the transmitted MLT-3 signal can be
controlled to reduce EMI emissions. The MLT-3
signal after the magnetic has a typical rise/fall time of
approximately 4 ns, which is within the target range
specified in the ANSI TP- PMD standard. This is
guaranteed with either 1:1 or 1.25:1 transformer.
Receive Function
The 100Base-TX receive path functions as the
inverse of the transmit path. The receive path
includes a receiver with adaptive equalization and
DC restoration in the front end. It also includes a
MLT-3 to NRZI converter, 125 MHz data and clock
recovery, NRZI/NRZ conversion, Serial-to-Parallel
conversion, de-scrambler, and 5B/4B decoder. The
receiver circuit starts with a DC bias for the
differential RX+/- inputs, followed with a low-pass
filter to filter out high frequency noise from the
transmission channel media. An energy detect circuit
is also added to determine whether there is any signal
energy on the media. This is useful in the power-
saving mode. The amplification ratio and slicer’s
threshold is set by the on-chip bandgap reference.
When Dis_Scrm is set to “0” the data scrambling
function is disabled, the 5-bit data stream is clocked
directly to the device’s PMA sublayer.
Parallel to Serial, NRZ to NRZI, and MLT3
Conversion
The 5-bit NRZ data is clocked into Phy’s shift
register with a 25 MHz clock, and clocked out with a
125 MHz clock to convert it into a serial bit stream.
The serial data is converted from NRZ to NRZI
format, which produces a transition on Logic 1 and
no transition on Logic 0. To further reduce EMI
emissions, the NRZI data is converted to an MLT-3
signal. The conversion offers a 3dB to 6dB reduction
in EMI emissions. This allows system designers to
meet the FCC Class B ilmit. Whenever there is a
transition occurring in NRZI data, there is a
corresponding transition occurring in the MLT-3
data. For NRZI data, it changes the count up/down
direction after every single transition. For MLT-3
data, it changes the count up/down direction after
every two transitions. The NRZI to MLT-3 data
conversion is implemented without reference to the
bit timing or clock information. The conversion
requires detecting the transitions of the incoming
NRZI data and setting the count up/down direction
Baseline Wander Compensation
The 100Base-TX data stream is not always DC
balanced. The transformer blocks the DC components
of the incoming signal, thus the DC offset of the
differential receive inputs can drift. The shifting of
the signal level, coupled with non-zero rise and fall
times of the serial stream can cause pulse-width
distortion. This creates jitter and possible increase in
the bit error rates. Therefore, a DC restoration circuit
is needed to compensate for the attenuation of the DC
component. This Phy implements a patent-pending
DC restoration circuit. Unlike the traditional
implementation, the circuit does not need the
feedback information from the slicer or the clock
recovery circuit. This design simplifies the circuit
design and eliminates any random/systematic offset
on the receive path. In the 10BaseT and the 100Base-
FX modes, the baseline wander correction circuit is
not required, and therefore is disabled.
Clock/Data Recovery
The equalized MLT-3 signal passes through the slicer
circuit, and gets converted to NRZI format. The Phy
uses a proprietary mixed-signal phase locked loop
(PLL) to extract clock information from the incoming
NRZI data. The extracted clock is used to re-time the
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