SI5321 Datasheet, PDF (18/34 Pages) List of Unclassifed Manufacturers – SONET/SDH PRECISION CLOCK MULTIPLIER IC

Si5321
and setting FEC[2:0] = 001 (255/238 FEC scaling).
Finally, a 622.08 MHz output clock (a non-FEC rate) can
be generated from a 20.83 MHz input clock (an FEC
rate) by setting INFRQSEL[2:0] = 001 (19.44 MHz
range), setting FRQSEL[2:0] = 011 (32x multiplication)
and setting FEC[2:0] = 010 (238/255 FEC scaling).
.
Jitter
Transfer
Jitter Out
Jitter In
(s)
0 dB
2.3. PLL Performance
J_p Peaking
–20 dB/dec.
The Si5321 PLL provides extremely low jitter
generation, high jitter tolerance, and a well-controlled
jitter transfer function with low peaking and a high
degree of jitter attenuation.
2.3.1. Jitter Generation
Jitter generation is defined as the amount of jitter
produced at the output of the device with a jitter free
input clock. Generated jitter arises from sources within
the VCO and other PLL components. Jitter generation is
a function of the PLL bandwidth setting. Higher loop
bandwidth settings may result in lower jitter generation
but may also result in less attenuation of jitter than
might be present on the input clock signal.
2.3.2. Jitter Transfer
Jitter transfer is defined as the ratio of output signal jitter
to input signal jitter for a specified jitter frequency. The
jitter transfer characteristic determines the amount of
input clock jitter that passes to the outputs. The DSPLL
technology used in the Si5321 provides tightly-
controlled jitter transfer curves because the PLL gain
parameters are determined by digital circuits that do not
vary over supply voltage, process, and temperature. In
a system application, a well-controlled transfer curve
minimizes the output clock jitter variation from board to
board and provides more consistent system level jitter
performance.
The jitter transfer characteristic is a function of the
BWSEL[1:0] setting. Lower bandwidth settings result in
more jitter attenuation of the incoming clock but may
result in higher jitter generation. Table 4 on page 10
gives the 3 dB bandwidth and peaking values for
specified BWSEL settings. Figure 6 shows the jitter
transfer curve mask.
F_BW
f_Jitter
Figure 6. PLL Jitter Transfer Mask/Template
2.3.3. Jitter Tolerance
Jitter tolerance for the Si5321 is defined as the
maximum peak-to-peak sinusoidal jitter that can be
present on the incoming clock. The tolerance is a
function of the jitter frequency because tolerance
improves for lower input jitter frequency.
Input
Jitter
A m p litu d e
–20 dB/dec.
10 ns
Excessive Input Jitter Range
F_BW
f_{Jitter In}
Figure 7. Jitter Tolerance Mask/Template
2.4. Loss-of-Signal Alarm
The Si5321 has loss-of-signal (LOS) circuitry that
constantly monitors the CLKIN input clock for missing
pulses. The LOS circuitry sets a LOS output alarm
signal when missing pulses are detected.
The LOS circuitry operates as follows. Regardless of
the selected input clock frequency range, the LOS
circuitry divides down the input clock into the 19 MHz
range. The LOS circuitry then over-samples this divided
down input clock to search for extended periods of time
without input clock transitions. If the LOS circuitry
detects four consecutive samples of the divided down
input clock that are the same state (i.e., 1111 or 0000), a
LOS condition is declared; the Si5321 goes into digital
hold mode, and the LOS output alarm signal is set high.
The LOS sampling circuitry runs at a frequency of f_{O_78},
where f_{O_78} is the output clock frequency when the
FRQSEL[2:0] pins are set to 100. Figure 3 on page 5
and Table 3 on page 7 list the minimum and maximum
transitionless time periods required for declaring a LOS
on the input clock (t_LOS).
Rev. 2.3
19