SI5321 Datasheet, PDF (17/34 Pages) List of Unclassifed Manufacturers – SONET/SDH PRECISION CLOCK MULTIPLIER IC

Si5321
The Si5321 clock input frequencies are variable within
the range specified in Table 3 on page 7. The output
rates are scaled accordingly. If a 19.44 MHz input clock
is used, the clock output frequency is 19.44, 38.88,
77.76, 155.52 MHz, etc.
Table 7. Loop Bandwidth and FEC Settings
External Inputs
BWSEL FEC
BWBOOST [1:0] [2:0]
0
00 000
0
00 001
0
00 010
0
00 011
0
00 100
0
00 101
0
00 110
0
00
111
0
10 000
0
10 001
0
10 010
0
10 011
0
10 100
0
10 101
0
10 110
0
10
111
0
11
000
0
11
001
0
11
010
0
11
011
0
11
100
0
11
101
0
11
110
0
11
111
1
00
0xx
1
10
0xx
1
11
0xx
1
01
0xx
0
01 000
0
01 001
0
01 010
0
01 011
0
01 100
0
01 101
0
01 110
0
01
111
Effective
FEC
Conversion
Rate
1/1
255/238
238/255
Reserved
255/237
237/255
66/64
64/66
1/1
255/238
238/255
Reserved
255/237
237/255
66/64
64/66
1/1
255/238
238/255
Reserved
255/237
237/255
66/64
64/66
1/1
1/1
1/1
1/1
1/1
255/238
238/255
Reserved
255/237
237/255
66/64
64/66
Effective
PLL
Bandwidth
(Hz)
3200
3200
3200
—
3200
3200
3200
3200
800
800
800
—
800
800
800
800
6400
6400
6400
—
6400
6400
6400
6400
6400
1600
12800
3200
1600
1600
1600
—
1600
1600
1600
1600
Table 8. Nominal Clock Input Frequencies
Input Clock
Frequency
Range
Reserved
622 MHz
311 MHz
155 MHz
77 MHz
38 MHz
19 MHz
Reserved
INFRQSEL2 INFRQSEL1 INFRQSEL0
1
1
1
1
1
0
1
0
1
1
0
0
0
1
1
0
1
0
0
0
1
0
0
0
Table 9. Nominal Clock Output Frequencies
Output Clock
Frequency
Range
2,488.32 MHz
1244.16 MHz
622.08 MHz
311.04 MHz
155.52 MHz
77.76 MHz
38.88 MHz
19.44 MHz
FRQSEL2
1
1
0
1
0
1
0
0
FRQSEL1
1
1
1
0
1
0
0
0
FRQSEL0
1
0
1
1
0
0
0
1
2.2.1. FEC Rate Conversion
The Si5321 provides a 1/32x, 1/16x, 1/8x, 1/4x, 1/2x,
1x, 2x, 4x, 8x, 16x, 32x, 64x, or 128x clock frequency
multiplication function with an option for additional
forward or reverse frequency scaling by a factor of 255/
238 (15/14), 255/237 (85/79), or 66/64 (33/32) for FEC
rate conversion applications. The 255/237 and the 66/
64 rate conversions requires the input clock rate to be in
the 155 MHz or higher ranges. The multiplication factor
is configured by selecting the input and output clock
frequency ranges for the device. The additional
frequency scaling for FEC rate conversion is selected
using the FEC[2:0] control inputs.
For example, a 622.08 MHz output clock (a non-FEC
rate) can be generated from a 19.44 MHz input clock (a
non-FEC rate) by setting INFRQSEL[2:0] = 001
(19.44 MHz range), setting FRQSEL[2:0] = 011 (32x
multiplication) and setting FEC[2:0] = 000 (no FEC
scaling). A 666.51 MHz output clock (an FEC rate) can
be generated from a 19.44 MHz input clock (a non-FEC
rate) by setting INFRQSEL[2:0] = 001 (19.44 MHz
range), setting FRQSEL[2:0] = 011 (32x multiplication)
18
Rev. 2.3