QL4016-1PB456M Datasheet, PDF (17/22 Pages) List of Unclassifed Manufacturers – 90,000 Usable PLD Gate QuickRAM Combining Performance, Density and Embedded RAM

Military QuickRAM
QL4036
QL4036
AC CHARACTERISTICS at VCC = 3.3V, TA = 25°C (K = 1.00)
(To calculate delays, multiply the appropriate K factor in the "Operating Range" section by the following numbers.)
Logic Cells
Symbol
Parameter
tPD
tSU
tH
tCLK
tCWHI
tCWLO
tSET
tRESET
tSW
tRW
Combinatorial Delay [6]
Setup Time [6]
Hold Time
Clock to Q Delay
Clock High Time
Clock Low Time
Set Delay
Reset Delay
Set Width
Reset Width
Propagation Delays (ns)
Fanout [5]
1
2
3
4
8
1.4
1.7
1.9
2.2
3.2
1.7
1.7
1.7
1.7
1.7
0.0
0.0
0.0
0.0
0.0
0.7
1.0
1.2
1.5
2.5
1.2
1.2
1.2
1.2
1.2
1.2
1.2
1.2
1.2
1.2
1.0
1.3
1.5
1.8
2.8
0.8
1.1
1.3
1.6
2.6
1.9
1.9
1.9
1.9
1.9
1.8
1.8
1.8
1.8
1.8
Symbol
TIN
TINI
TISU
TIH
TlCLK
TlRST
TlESU
TlEH
Input-Only/Clock Cells
Parameter
High Drive Input Delay
High Drive Input, Inverting Delay
Input Register Set-Up Time
Input Register Hold Time
Input Register Clock To Q
Input Register Reset Delay
Input Register Clock Enable Setup Time
Propagation Delays (ns)
Fanout [5]
1
2
3
4
8 12 24
1.5 1.6 1.8 1.9 2.4 2.9 4.4
1.6 1.7 1.9 2.0 2.5 3.0 4.5
3.1 3.1 3.1 3.1 3.1 3.1 3.1
0.0 0.0 0.0 0.0 0.0 0.0 0.0
0.7 0.8 1.0 1.1 1.6 2.1 3.6
0.6 0.7 0.9 1.0 1.5 2.0 3.5
2.3 2.3 2.3 2.3 2.3 2.3 2.3
Input Register Clock Enable Hold Time 0.0 0.0 0.0 0.0 0.0 0.0 0.0
Notes:
[5] Stated timing for worst case Propagation Delay over process variation at VCC=3.3V and TA=25°C. Multi-
ply by the appropriate Delay Factor, K, for speed grade, voltage and temperature settings as specified in the
Operating Range.
[6] These limits are derived from a representative selection of the slowest paths through the pASIC 3 logic cell
including typical net delays. Worst case delay values for specific paths should be determined fromtiming
analysis of your particular design.
Rev A
8-53