QL4016-1PB456M Datasheet, PDF (16/22 Pages) List of Unclassifed Manufacturers – 90,000 Usable PLD Gate QuickRAM Combining Performance, Density and Embedded RAM

Military QuickRAM
Symbol
tACK
tGCKP
tGCKB
QL4016 Clock Cells
Parameter
Array Clock Delay
Global Clock Pin Delay
Global Clock Buffer Delay
Propagation Delays (ns)
Loads per Half Column [8]
1 2 3 4 8 10 11
1.2 1.2 1.3 1.3 1.5 1.6 1.7
0.7 0.7 0.7 0.7 0.7 0.7 0.7
0.8 0.8 0.9 0.9 1.1 1.2 1.3
I/O Cell Input Delays
Symbol
tI/O
TISU
TIH
TlOCLK
TlORST
TlESU
TlEH
Parameter
Input Delay (bidirectional pad)
Input Register Set-Up Time
Input Register Hold Time
Input Register Clock To Q
Input Register Reset Delay
Input Register clock Enable Set-Up Time
Input Register Clock Enable Hold Time
Propagation Delays (ns)
Fanout [6]
1
2
3
4
8
10
1.3 1.6 1.8 2.1 3.1 3.6
3.1 3.1 3.1 3.1 3.1 3.1
0.0 0.0 0.0 0.0 0.0 0.0
0.7 1.0 1.2 1.5 2.5 3.0
0.6 0.9 1.1 1.4 2.4 2.9
2.3 2.3 2.3 2.3 2.3 2.3
0.0 0.0 0.0 0.0 0.0 0.0
Symbol
TOUTLH
TOUTHL
TPZH
TPZL
TPHZ
TPLZ
I/O Cell Output Delays
Parameter
Output Delay Low to High
Output Delay High to Low
Output Delay Tri-state to High
Output Delay Tri-state to Low
Output Delay High to Tri-State [9]
Output Delay Low to Tri-State [9]
Propagation Delays (ns)
Output Load Capacitance (pF)
30
50
75
100
150
2.1
2.5
3.1
3.6
4.7
2.2
2.6
3.2
3.7
4.8
1.2
1.7
2.2
2.8
3.9
1.6
2.0
2.6
3.1
4.2
2.0
1.2
Notes:
[6] Stated timing for worst case Propagation Delay over process variation at VCC=3.3V and TA=25°C.
Multiply by the appropriate Delay Factor, K, for speed grade, voltage and temperature settings as
specified in the Operating Range.
[8] The array distributed networks consist of 40 half columns and the global distributed networks consist of
44 half columns, each driven by an independent buffer. The number of half columns used does not
affect clock buffer delay. The array clock has up to 8 loads per half column. The global clock has up to
11 loads per half column.
[9] The following loads are used for tPXZ:
tPHZ
1KΩ
1KΩ
5 pF
tPLZ
5 pF
8-52
Rev A
52
Preliminary