OX9162 Datasheet, PDF (14/41 Pages) List of Unclassifed Manufacturers – Integrated Parallel Port/Local Bus and PCI interface

OXFORD SEMICONDUCTOR LTD.
OX9162
Bits
Description
Read/Write
EEPROM PCI
Reset
These bits are unused in Motorola-type interface.
15:12
Write Chip-select De-assertion (Intel-type interface). Defines the number
W
RW
2h
of clock cycles after the reference cycle when the LBCS[1:0]# pins are
de-asserted (high) during a write operation to the Local Bus. ¹
Read-not-Write De-assertion during write cycles (Motorola-type
interface). Defines the number of clock cycles after the reference cycle
when the LBRDWR# pin is de-asserted (high) during a write to the Local
Bus. ¹
19:16
Read Control Assertion (Intel-type interface). Defines the number of
W
RW
0h
clock cycles after the Reference Cycle when the LBRD# pin is asserted
(1h for
(low) during a read from the Local Bus. ¹
parallel port)
Read Data-strobe Assertion (Motorola-type interface). Defines the
number of clock cycles after the Reference Cycle when the LBDS[1:0]#
pins are asserted (low) during a read from the Local Bus. ¹
23:20
Read Control De-assertion (Intel-type interface). Defines the number of
W
RW
3h
clock cycles after the Reference Cycle when the LBRD# pin is de-
(2h for
asserted (high) during a read from the Local Bus. ¹
parallel port)
Read Data-strobe De-assertion (Motorola-type interface). Defines the
number of clock cycles after the Reference Cycle when the LBDS[1:0]#
pins are de-asserted (high) during a read from the Local Bus. ¹
27:24
Write Control Assertion (Intel-type interface). Defines the number of
W
RW
0h
clock cycles after the Reference Cycle when the LBWR# pin is asserted
(1h for
(low) during a write to the Local Bus. ¹
parallel port)
Write Data-strobe Assertion (Motorola-type interface). Defines the
number of clock cycles after the Reference Cycle when the LBDS[1:0]#
pins are asserted (low) during a write to the Local Bus. ¹
31:28
Write Control De-assertion (Intel-type interface). Defines the number of
W
RW
2h
clock cycles after the Reference Cycle when the LBWR# pin is de-
asserted (high) during a write to the Local Bus. ¹
Write Data-strobe De-assertion (Motorola-type interface). Defines the
number of clock cycles after the Reference Cycle when the LBDS[1:0]#
pins are de-asserted (high) during a write cycle to the Local Bus. ¹
Note 1: Only values in the range of 0h to Ah (0-10 decimal) are valid. Other values are reserved. See notes in the following page.
Data Sheet Revision 1.1 PRELIMINARY
Page 14