NT128D64S88A0G Datasheet, PDF (14/15 Pages) List of Unclassifed Manufacturers – 184pin One Bank Unbuffered DDR SDRAM MODULE

NT128D64S88A0G
128MB : 16M x 64
PC2100 / PC1600 Unbuffered DIMM
AC Timing for PC2100 - Applicable Specifications Expressed in Clock Cycles
( TA = 0 °C ~ 70 °C ; VDDQ = 2.5V ± 0.2V; VDD = 2.5V ± 0.2V, See AC Characteristics)
Symbol
Parameter
PC2100 @ CL = 2.5
Min.
Max.
Unit
Note
tMRD Mode register set command cycle time
2
tC K
1,2,3,4
tWPRE Write preamble
0.25
tC K
1,2,3,4
tRAS Active to Precharge command
6
16000
tC K
1,2,3,4
tRC
Active to Active/Auto-refresh command period
9
Auto-refresh to Active/Auto-refresh
tRFC
command period
10
tC K
1,2,3,4
tC K
1,2,3,4
tRCD Active to Read or Write delay
3
tC K
1,2,3,4
tRAP Active to Read Command with Autoprecharge
3
tC K
1,2,3,4
tR P
Precharge command period
3
tC K
1,2,3,4
tRRD Active bank A to Active bank B command
2
tC K
1,2,3,4
tWR
Write recovery time
2
tC K
1,2,3,4,5
tDAL Auto precharge write recovery + precharge time
5
tC K
1, 2, 3,4
tWTR Internal write to read command delay
1
tC K
1, 2, 3,4
tXSNR Exit self-refresh to non-read command
10
tC K
1, 2, 3,4
tXSRD Exit self-refresh to read command
200
tC K
1, 2, 3,4
1. Input slew rate = 1V/ns.
2. The CK/ CK input reference level (for timing reference to CK/ CK ) is the point at which CK and CK cross: the input reference level
for signals other than CK/ CK , is V REF.
3. Inputs are not recognized as valid until V REF stabilizes.
4. The Output timing reference level, as measured at the timing reference point indicated in AC Characteristics (Note 3) is V TT .
5. tHZ and t LZ transitions occur in the same access time windows as valid data transitions. These parameters are not referred to a
specific voltage level, but specify when the device is no longer driving (HZ), or begins driving (LZ).
REV1.0 / June 2001
14
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