NT128D64S88A0G Datasheet, PDF (11/15 Pages) List of Unclassifed Manufacturers – 184pin One Bank Unbuffered DDR SDRAM MODULE

NT128D64S88A0G
128MB : 16M x 64
PC2100 / PC1600 Unbuffered DIMM
AC Timing Specifications for DDR SDRAM Devices Used on Module
( TA = 0 °C ~ 70 °C ; VDDQ = 2.5V ± 0.2V; VDD = 2.5V ± 0.2V, See AC Characteristics) (Part 1 of 2)
Symbol
Parameter
-7K
Min. Max.
-75B
Min. Max.
-8B
Min. Max.
tAC
DQ output access time from CK/ CK
-0.75 +0.75 -0.75 +0.75 -0.8 +0.8
tDQSCK DQS output access time from CK/ CK
-0.75 +0.75 -0.75 +0.75 -0.8 +0.8
tCH
CK high-level width
0.45 0.55 0.45 0.55 0.45 0.55
tC L
CK low -level width
0.45 0.55 0.45 0.55 0.45 0.55
tC K
Clock cycle time
tC K
CL=2.5
CL=2
7
12
7.5
12
8
12
7.5
12
10
12
10
12
tDH
DQ and DM input hold time
0.5
0.5
0.6
tD S
DQ and DM input setup time
0.5
0.5
0.6
tDIPW DQ and DM input pulse width (each input)
1.75
1.75
2
tHZ
Data-out high-impedance time from CK/ CK
-0.75 +0.75 -0.75 +0.75 -0.8 +0.8
tLZ
Data-out low -impedance time from CK/ CK
-0.75 +0.75 -0.75 +0.75 -0.8 +0.8
tDQSQ
DQS-DQ skew (DQS & associated DQ
signals)
0.5
0.5
0.6
tDQSQA DQS-DQ skew (DQS & all DQ signals)
0.5
0.5
0.6
Minimum half clk period for any given cycle; tCH
tCH
tCH
tH P
defined by clk high(tCH )
or
or
or
or clk low (tCL ) time
tC L
tC L
tC L
tQH
Data output hold time from DQS
tHP -
0.75n
s
tHP -
0.75n
s
tHP -
1.0ns
tDQSS
Write command to 1st DQS latching
transition
0.75 1.25 0.75 1.25 0.75 1.25
DQS input low (high) pulse width
tDQSL,H
(write cycle)
0.35
0.35
0.35
DQS falling edge to CK setup time
tDSS
0.2
0.2
0.2
(write cycle)
DQS falling edge hold time from CK
tDSH
0.2
0.2
0.2
(write cycle)
tMRD Mode register set command cycle time
14
15
16
tWPRES Write preamble setup time
0
0
0
tWPST
tWPRE
tIH
Write postamble
Write preamble
Address and control input hold time
(fast slew rate)
Address and control input setup time
tI S
(fast slew rate)
Address and control input hold time
tIH
(slow slew rate)
0.40 0.60 0.40 0.60 0.40 0.60
0.25
0.25
0.25
0.9
1.1
1.1
0.9
1.1
1.1
1.0
1.1
1.1
Unit Notes
ns 1,2,3,4
ns 1,2,3,4
tCK 1,2,3,4
tCK 1,2,3,4
ns 1,2,3,4
ns 1,2,3,4
1,2,3,4
ns
, 18,19
1,2,3,4
ns
,18,19
ns 1,2,3,4
1, 2, 3,
ns
4, 5
1, 2, 3,
ns
4, 5
ns 1,2,3,4
ns 1,2,3,4
tCK 1,2,3,4
tCK 1,2,3,4
tCK 1,2,3,4
tCK 1,2,3,4
tCK 1,2,3,4
tCK 1,2,3,4
ns 1,2,3,4
1, 2, 3,
ns
4, 7
1, 2, 3,
tC K
4, 6
tCK 1,2,3,4
2, 3, 4,
ns 11, 13,
14
2, 3, 4,
ns 11, 13,
14
2, 3, 4,
ns 12, 13,
14, 17
REV1.0 / June 2001
11
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NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.