NT128D64S88A0G Datasheet, PDF (12/15 Pages) List of Unclassifed Manufacturers – 184pin One Bank Unbuffered DDR SDRAM MODULE

NT128D64S88A0G
128MB : 16M x 64
PC2100 / PC1600 Unbuffered DIMM
AC Timing Specifications for DDR SDRAM Devices Used on Module
( TA = 0 °C ~ 70 °C ; VDDQ = 2.5V ± 0.2V; VDD = 2.5V ± 0.2V, See AC Characteristics) (Part 2 of 2)
Symbol
Parameter
Address and control input setup time
tI S
(slow slewrate)
tIPW
Input pulse width
tRPRE Read preamble
-7K
Min.
Max.
1.0
2.2
0.9
1.1
-75B
Min.
Max.
1.0
2.2
0.9
1.1
-8B
Min.
Max.
1.1
-
0.9
1.1
Unit Notes
2, 3, 4,
ns ^{12, 13,}
14, 17
2, 3, 4,
ns
14
tCK 1,2,3,4
tRPST Read postamble
0.40
0.60
0.40
0.60
0.40
0.60
tCK 1,2,3,4
tRAS Active to Precharge command
45
120,000 45
120,000 50
120,000 ns 1,2,3,4
Active to Active/Auto-refresh
tRC
65
65
70
ns 1,2,3,4
command period
Auto-refresh to Active/Auto-refresh
tRFC
75
75
80
ns 1,2,3,4
command period
tRCD Active to Read or Write delay
20
20
20
ns 1,2,3,4
Active to Read Command with
tRAP
20
20
20
ns 1,2,3,4
Autoprecharge
tR P
Precharge command period
20
20
20
ns 1,2,3,4
tRRD
tWR
Active bank A to Active bank B
command
Write recovery time
Auto precharge write recovery +
tDAL
precharge time
15
15
(tWR/
tCK )
+
(tR P/
15
15
(tWR/
tCK )
+
(tRP /
15
15
(tWR/
tCK )
+
(tRP /
ns 1,2,3,4
ns 1,2,3,4
1, 2, 3,
tCK _{4, 16}
tCK )
tCK )
tCK )
tWTR Internal write to read command delay
1
1
1
tCK 1,2,3,4
Exit self-refresh to non-read
tXSNR
75
75
80
ns 1,2,3,4
command
tXSRD
tREFI
Exit self-refresh to read command
Average Periodic Refresh Interval
200
200
200
tCK 1,2,3,4
1, 2, 3,
15.6
15.6
15.6
µs
4, 8
REV1.0 / June 2001
12
© NANYA TECHNOLOGY CORP.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.