HWD2108 Datasheet, PDF (13/18 Pages) List of Unclassifed Manufacturers – Dual 105 mW Headphone Amplifier

Application Information
EXPOSED-DAP PACKAGE PCB MOUNTING
CONSIDERATION
The HWD2108’s exposed-dap (die attach paddle) package
(LD) provides a low thermal resistance between the die and
the PCB to which the part is mounted and soldered. This
allows rapid heat transfer from the die to the surrounding
PCB copper traces, ground plane, and surrounding air.
The LD package should have its DAP soldered to a copper
pad on the PCB. The DAP’s PCB copper pad may be con-
nected to a large plane of continuous unbroken copper. This
plane forms a thermal mass, heat sink, and radiation area.
However, since the HWD2108 is designed for headphone ap-
plications, connecting a copper plane to the DAP’s PCB
copper pad is not required. The HWD2108’s Power Dissipation
vs Output Power Curve in the Typical Performance Char-
acteristics shows that the maximum power dissipated is just
45mW per amplifier with a 5V power supply and a 32Ω load.
Further detailed and specific information concerning PCB
layout, fabrication, and mounting an LD (LLP) package is
available from CSMSC Semiconductor’s Package Engineer-
ing Group under application note AN1187.
POWER DISSIPATION
Power dissipation is a major concern when using any power
amplifier and must be thoroughly understood to ensure a
successful design. Equation 1 states the maximum power
dissipation point for a single-ended amplifier operating at a
given supply voltage and driving a specified output load.
P_DMAX = (V_DD) ² / (2π²R_L)
(1)
Since the HWD2108 has two operational amplifiers in one
package, the maximum internal power dissipation point is
twice that of the number which results from Equation 1. Even
with the large internal power dissipation, the HWD2108 does
not require heat sinking over a large range of ambient tem-
perature. From Equation 1, assuming a 5V power supply and
a 32Ω load, the maximum power dissipation point is 40mW
per amplifier. Thus the maximum package dissipation point
is 80mW. The maximum power dissipation point obtained
must not be greater than the power dissipation that results
from Equation 2:
P_DMAX = (T_JMAX − T_A) / θ_JA
(2)
For package MUA08A, θ_JA = 210˚C/W. T_JMAX = 150˚C for
the HWD2108. Depending on the ambient temperature,_AT, of
the system surroundings, Equation 2 can be used to find the
maximum internal power dissipation supported by the IC
packaging. If the result of Equation 1 is greater than that of
Equation 2, then either the supply voltage must be de-
creased, the load impedance increased or T_A reduced. For
the typical application of a 5V power supply, with a 32Ω load,
the maximum ambient temperature possible without violating
the maximum junction temperature is approximately 133.2˚C
provided that device operation is around the maximum
power dissipation point. Power dissipation is a function of
output power and thus, if typical operation is not around the
maximum power dissipation point, the ambient temperature
may be increased accordingly. Refer to the Typical Perfor-
mance Characteristics curves for power dissipation infor-
mation for lower output powers.
POWER SUPPLY BYPASSING
As with any power amplifier, proper supply bypassing is
critical for low noise performance and high power supply
rejection. Applications that employ a 5V regulator typically
use a 10µF in parallel with a 0.1µF filter capacitors to stabi-
lize the regulator’s output, reduce noise on the supply line,
and improve the supply’s transient response. However, their
presence does not eliminate the need for a local 0.1µF
supply bypass capacitor, C_S, connected between the
HWD2108’s supply pins and ground. Keep the length of leads
and traces that connect capacitors between the HWD2108’s
power supply pin and ground as short as possible. Connect-
ing a 1.0µF capacitor, C_B, between the IN A(+) / IN B(+) node
and ground improves the internal bias voltage’s stability and
improves the amplifier’s PSRR. The PSRR improvements
increase as the bypass pin capacitor value increases. Too
large, however, increases the amplifier’s turn-on time. The
selection of bypass capacitor values, especially C_B, depends
on desired PSRR requirements, click and pop performance
(as explained in the section, Selecting Proper External
Components), system cost, and size constraints.
SELECTING PROPER EXTERNAL COMPONENTS
Optimizing the HWD2108’s performance requires properly se-
lecting external components. Though the HWD2108 operates
well when using external components with wide tolerances,
best performance is achieved by optimizing component val-
ues.
The HWD2108 is unity-gain stable, giving a designer maximum
design flexibility. The gain should be set to no more than a
given application requires. This allows the amplifier to
achieve minimum THD+N and maximum signal-to-noise ra-
tio. These parameters are compromised as the closed-loop
gain increases. However, low gain demands input signals
with greater voltage swings to achieve maximum output
power. Fortunately, many signal sources such as audio
CODECs have outputs of 1V_RMS (2.83V_P-P). Please refer to
the Audio Power Amplifier Design section for more infor-
mation on selecting the proper gain.
Input and Output Capacitor Value Selection
Amplifying the lowest audio frequencies requires high value
input and output coupling capacitors (C_I and C_O in Figure 1).
A high value capacitor can be expensive and may compro-
mise space efficiency in portable designs. In many cases,
however, the speakers used in portable systems, whether
internal or external, have little ability to reproduce signals
below 150Hz. Applications using speakers with this limited
frequency response reap little improvement by using high
value input and output capacitors.
Besides affecting system cost and size, C_i has an effect on
the HWD2108’s click and pop performance. The magnitude of
the pop is directly proportional to the input capacitor’s size.
Thus, pops can be minimized by selecting an input capacitor
value that is no higher than necessary to meet the desired
−3dB frequency.
As shown in Figure 1, the input resistor, R_I and the input
capacitor, C_I, produce a −3dB high pass filter cutoff fre-
quency that is found using Equation (3). In addition, the
output load R_L, and the output capacitor C_O, produce a -3db
high pass filter cutoff frequency defined by Equation (4).
f_I-3db=1/2πR_IC_I
(3)
f_O-3db=1/2πR_LC_O
(4)
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