CS18LV02565 Datasheet, PDF (12/14 Pages) List of Unclassifed Manufacturers – HIGH SPEED SUPER LOW POWER SRAM

High Speed Super Low Power SRAM
32K-Word By 8 Bit
CS18LV02565
NOTES:
1. /WE must be high during address transitions.
2. The internal write time of the memory is defined by the overlap of /CE and /WE low. All signals must be active
to initiate a write and any one signal can terminate a write by going inactive. The data input setup and hold
timing should be referenced to the second transition edge of the signal that terminates the write.
3. T_WR is measured from the earlier of /CE or /WE going high at the end of write cycle.
4. During this period, DQ pins are in the output state so that the input signals of opposite phase to the outputs
must not be applied.
5. If the /CE low transition occurs simultaneously with the /WE low transitions or after the /WE transition, output
remain in a high impedance state.
6. /OE is continuously low (/OE = V_IL ).D_OUT is the same phase of write data of this write cycle.
7. D_OUT is the read data of next address.
8. If /CE is low during this period, DQ pins are in the output state. Then the data input signals of opposite phase
to the outputs must not be applied to them.
9. Test conditions assume signal transition times of 5ns or less, timing reference levels of 0.5VCC, input pulse
levels of 0V to VCC and output loading specified in Figure 1A.
10. Transition is measured ±500mV from steady state with C_L = 5pF as shown in Figure 1B. The parameter is
guaranteed but not 100% tested.
11. T_CW is measured from the later of /CE going low to the end of write.
ORDER INFORMATION
12
Rev. 2.0
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