U635H64 Datasheet, PDF (11/13 Pages) List of Unclassifed Manufacturers – POWER STORE 8K X 8 NVSRAM

U635H64
Device Operation
The U635H64 has two separate modes of operation:
SRAM mode and nonvolatile mode. In SRAM mode,
the memory operates as a standard fast static RAM. In
nonvolatile mode, data is transferred from SRAM to
EEPROM (the STORE operation) or from EEPROM to
SRAM (the RECALL operation). In this mode SRAM
functions are disabled.
STORE cycles may be initiated under user control via a
software sequence and are also automatically initiated
when the power supply voltage level of the chip falls
below V_SWITCH. RECALL operations are automatically
initiated upon power up and may occur also when V_CC
rises above V_SWITCH after a low power condition.
RECALL cycles may also be initiated by a software
sequence.
SRAM READ
The U635H64 performs a READ cycle whenever E and
G are LOW and W are HIGH. The address specified on
pins A0 - A12 determines which of the 8192 data bytes
will be accessed. When the READ is initiated by an
address transition, the outputs will be valid after a delay
of t_cR. If the READ is initiated by E or G, the outputs will
be valid at t_a(E) or at t_a(G), whichever is later. The data
outputs will repeatedly respond to address changes
within the t_cR access time without the need for transition
on any control input pins, and will remain valid until
another address change or until E or G is brought
HIGH or W is brought LOW.
SRAM WRITE
A WRITE cycle is performed whenever E and W are
LOW. The address inputs must be stable prior to
entering the WRITE cycle and must remain stable until
either E or W goes HIGH at the end of the cycle. The
data on pins DQ0 - 7 will be written into the memory if it
is valid t_su(D) before the end of a W controlled WRITE or
t_su(D) before the end of an E controlled WRITE.
It is recommended that G is kept HIGH during the en-
tire WRITE cycle to avoid data bus contention on the
common I/O lines. If G is left LOW, internal circuitry will
turn off the output buffers t_dis(W) after W goes LOW.
Automatic STORE
The U635H64 uses the intrinsic system capacitance to
perform an automatic STORE on power down. As long
as the system power supply take at least t_PDSTORE to
decay from V_SWITCH down to 3.6 V the U635H64 will
safely and automatically STORE the SRAM data in
EEPROM on power down.
In order to prevent unneeded STORE operations, auto-
matic STORE will be ignored unless at least one
WRITE operation has taken place since the most
recent STORE or RECALL cycle. Software initiated
STORE cycles are performed regardless of whether or
not a WRITE operation has taken place.
Automatic RECALL
During power up an automatic RECALL takes place.
After any low power condition (V_CC < V_SWITCH) an inter-
nal RECALL request may be latched. When V_CC once
again exceeds the sense voltage of V_SWITCH, a reque-
sted RECALL cycle will automatically be initiated and
will take t_RESTORE to complete.
If the U635H64 is in a WRITE state at the end of a
power up RECALL, the SRAM data will be corrupted.
To help avoid this situation, a 10 KΩ resistor should be
connected between W and system V_CC.
Software Nonvolatile STORE
The U635H64 software controlled STORE cycle is
initiated by executing sequential READ cycles from six
specific address locations. By relying on READ cycles
only, the U635H64 implements nonvolatile operation
while remaining compatible with standard 8K x 8
SRAMs. During the STORE cycle, an erase of the pre-
vious nonvolatile data is performed first, followed by a
parallel programming of all nonvolatile elements. Once
a STORE cycle is initiated, further inputs and outputs
are disabled until the cycle is completed.
Because a sequence of addresses is used for STORE
initiation, it is important that no other READ or WRITE
accesses intervene in the sequence or the sequence
will be aborted.
To initiate the STORE cycle the following READ
sequence must be performed:
1. Read address 0000 (hex) Valid READ
2. Read address 1555 (hex) Valid READ
3. Read address 0AAA (hex) Valid READ
4. Read address 1FFF (hex) Valid READ
5. Read address 10F0 (hex) Valid READ
6. Read address 0F0F (hex) Initiate STORE
Once the sixth address in the sequence has been
entered, the STORE cycle will commence and the chip
will be disabled. It is important that READ cycles and
not WRITE cycles are used in the sequence, although it
is not necessary that G is LOW for the sequence to be
valid. After the t_STORE cycle time has been fulfilled, the
SRAM will again be activated for READ and WRITE
operation.
April 7, 2005
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