U635H64 Datasheet, PDF (1/13 Pages) List of Unclassifed Manufacturers – POWER STORE 8K X 8 NVSRAM

U635H64
PowerStore 8K x 8 nvSRAM
Features
S High-performance CMOS non-
volatile static RAM 8192 x 8 bits
S 25, 35 and 45 ns Access Times
S 12, 20 and 25 ns Output Enable
Access Times
S I_CC = 15 mA at 200 ns Cycle
Time
S Automatic STORE to EEPROM
on Power Down using system
capacitance
S Software initiated STORE
(STORE Cycle Time < 10 ms)
S Automatic STORE Timing
S 10⁵ STORE cycles to EEPROM
S 10 years data retention in
EEPROM
S Automatic RECALL on Power Up
S Software RECALL Initiation
(RECALL Cycle Time < 20 µs)
S Unlimited RECALL cycles from
EEPROM
S Single 5 V ± 10 % Operation
S Operating temperature ranges:
0 to 70 °C
-40 to 85 °C
S QS 9000 Quality Standard
S ESD characterization according-
MIL STD 883C M3015.7-HBM
(classification see IC Code
Numbers)
S RoHS compliance and Pb- free
S Packages: PDIP28 (600 mil)
SOP28 (330 mil)
Description
The U635H64 has two separate
modes of operation: SRAM mode
and nonvolatile mode. In SRAM
mode, the memory operates as an
ordinary static RAM. In nonvolatile
operation, data is transferred in
parallel from SRAM to EEPROM or
from EEPROM to SRAM. In this
mode SRAM functions are disab-
led.
The U635H64 is a fast static RAM
(25, 35, 45 ns), with a nonvolatile
electrically erasable PROM
(EEPROM) element incorporated
in each static memory cell. The
SRAM can be read and written an
unlimited number of times, while
independent nonvolatile data resi-
des in EEPROM. Data transfers
from the SRAM to the EEPROM
(the STORE operation) take place
automatically upon power down
using charge stored in system
capacitance.
Transfers from the EEPROM to the
SRAM (the RECALL operation)
take place automatically on power
up. The U635H64 combines the
high performance and ease of use
of a fast SRAM with nonvolatile
data integrity.
STORE cycles also may be initia-
ted under user control via a soft-
ware sequence.
Once a STORE cycle is initiated,
further input or output are disabled
until the cycle is completed.
Because a sequence of addresses
is used for STORE initiation, it is
important that no other read or write
accesses intervene in the
sequence or the sequence will be
aborted.
RECALL cycles may also be initia-
ted by a software sequence.
Internally, RECALL is a two step
procedure. First, the SRAM data is
cleared and second, the nonvolatile
information is transferred into the
SRAM cells.
The RECALL operation in no way
alters the data in the EEPROM
cells. The nonvolatile data can be
recalled an unlimited number of
times.
Pin Configuration
Pin Description
n.c.
A12
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
DQ1
DQ2
VSS
1
28
2
27
3
26
4
25
5
24
6
23
7 PDIP 22
8 SOP 21
9
20
10
19
11
18
12
17
13
16
14
15
Top View
VCC
W
n.c.
A8
A9
A11
G
A10
E
DQ7
DQ6
DQ5
DQ4
DQ3
April 7, 2005
Signal Name
A0 - A12
DQ0 - DQ7
E
G
W
VCC
VSS
Signal Description
Address Inputs
Data In/Out
Chip Enable
Output Enable
Write Enable
Power Supply Voltage
Ground
1