N32T1630C1E Datasheet, PDF (10/14 Pages) List of Unclassifed Manufacturers – 32Mb Ultra-Low Power Asynchronous CMOS PSRAM

NanoAmp Solutions, Inc.
Power Savings Modes
The three low power modes are:
• Reduced Memory Size
• Partial Array Refresh
• Deep Sleep Mode
N32T1630C1E
The operation of the power saving modes is controlled by setting the Variable Address Register (VAR).
This VAR is shown in the following “Variable Address Register” figure and is used to enable/disable the
various low power modes. The VAR is set by using the timings defined in the figure titled “Variable
Address Register (VAR) Update Timings”. The register must be set in less then 1us after ZZ is enabled
low.
1) Reduced Memory Size (RMS)
In this mode of operation, the 32Mb PSRAM can be operated as a 8Mb or 16Mb device. The mode and
array size are determined by the settings in the VA register. The VA register is set according to the follow-
ing timings and the bit settings in the table “Address Patterns for RMS”. The RMS mode is enabled at the
time of ZZ transitioning high and the mode remains active until the register is updated. To return to the full
32Mb address space, the VA register must be reset using the previously defined procedures. While oper-
ating in the RMS mode, the unselected portion of the array may not be used.
2) Partial Array Refresh (PAR)
In this mode of operation, the internal refresh operation can be restricted to a 8Mb or 16Mb portion of the
array. The mode and array partition to be refreshed are determined by the settings in the VA register. The
VA register is set according to the following timings and the bit settings in the table “Address Patterns for
PAR”. In this mode, when ZZ is active low, only the portion of the array that is set in the register is
refreshed. The operating mode is only available during standby time (ZZ low) and once ZZ is returned
high, the device resumes full array refresh. All future PAR cycles will use the contents of the VA register
that has been previously set. To change the address space of the PAR mode, the VA register must be
reset using the previously defined procedures.
3) Deep Sleep Mode
In this mode of operation, the internal refresh is turned off and all data integrity of the array is lost. Deep
Sleep is entered by bringing ZZ low with the A4 register programmed to “Deep Sleep Enabled”. The
device will remain in this mode as long as ZZ remains low and when ZZ is driven high, all register settings
will return to default states.
(DOC # 14-02-006 Rev C ECN 01-1040
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The specifications of this device are subject to change without notice. For latest documentation see http://www.nanoamp.com.