ES3210 Datasheet, PDF (3/4 Pages) ESS Technology,Inc – Video CD Processor Product Brief

ES3210 PRODUCT BRIEF
ES3210 PIN DESCRIPTION
A
Table 1 ES3210 Pin Description (Continued)
Name
Number
I/O
Definition
PCLK
44
I/O Pixel clock qualifier in for screen video interface.
AUX[7:0]
54:52, 49:45 I/O Auxiliary control pins (AUX0 and AUX1 are open collectors).
LD[7:0]
62:55
I/O RISC interface data bus.
LWR#
63
O RISC interface write enable (active low).
LOE#
64
O RISC interface output enable (active low).
LCS[3,1,0]#
65:67
O RISC interface chip select (active low).
LA[17:0]
87:82, 79:68 O RISC interface address bus.
VPP
81
I Digital supply voltage for 5V.
ACLK
88
I/O Master clock for external audio DAC (8.192 MHz, 11.2896 MHz, 12.288 MHz, 16.9344
MHz, and 18.432 MHz).
AOUT/
89
O Dual-purpose pin. AOUT is the audio interface serial data output
SEL_PLL0
I Select PLL[0] input. The matrix below lists the available clock frequencies and their
respective PLL bit settings.
SEL_PLL1 SEL_PLL0 Clock Output
0
0
Bypass PLL
0
1
54.0 MHz
1
0
67.5 MHz
1
1
81.0 MHz
ATCLK
ATFS
SEL_PLL1
DOE#
AIN
ARCLK
ARFS
TDMCLK
TDMDR
TDMFS
CAS#
90
I/O Audio transmit bit clock.
91
O Audio transmit frame sync.
I Refer to the description and matrix for SEL_PLL0 pin 89.
92
O DRAM output enable (active low).
93
I Audio serial data input.
94
I Audio receive bit clock.
95
I Audio receive frame sync.
96
I TDM interface serial clock.
97
I TDM interface serial data receive.
98
I TDM interface frame sync.
99
O DRAM column address strobe bank 0 (active low).
ESS Technology, Inc.
SAM0417-051701
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