ES3210 Datasheet, PDF (2/4 Pages) ESS Technology,Inc – Video CD Processor Product Brief

A
ES3210 PINOUT
Figure 1 shows the ES3210 device pinout.
ES3210 PRODUCT BRIEF
ES3210 PINOUT
VPP
LA12
LA13
LA14
LA15
LA16
LA17
ACLK
AOUT/SEL_PLL0
ATCLK
ATFS/SEL_PLL1
DOE#
AIN
ARCLK
ARFS
TDMCLK
TDMDR
TDMFS
CAS#
VSS
8180 ^{79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 5150}
82
49
83
48
84
47
85
46
86
45
87
44
88
43
89
90
ES3210
42
41
91
40
92
93
100-pin PQFP
39
38
94
37
95
36
96
35
97
34
98
33
99
32
100
31
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
VSS
AUX4
AUX3
AUX2
AUX1
AUX0
PCLK
PCLK2X
CPUCLK
HSYNC
VSYNC
YUV7
YUV6
YUV5
YUV4
YUV3
YUV2
YUV1
YUV0
VDD
Figure 1 ES3210 Pinout Diagram
ES3210 PIN DESCRIPTION
Table 1 lists the ES3210 pin descriptions.
Table 1 ES3210 Pin Description
Name
Number
I/O
VDD
1, 31, 51
I
RAS#
2
O
DWE#
3
O
MA[8:0]
12:4
O
DBUS[15:0]
28:13
I/O
RESET#
29
I
VSS
30, 50, 80, 100 I
YUV[7:0]
39:32
O
VSYNC
40
I/O
HSYNC
41
I/O
CPUCLK
42
I
PCLK2X
43
I/O
Definition
Voltage supply for 3.3V.
DRAM row address strobe (active low).
DRAM write enable (active low).
DRAM multiplexed row and column address bus.
DRAM data bus I/O [15:0].
System reset (active low).
Ground.
YUV[7:0] pixel output data.
Vertical sync for screen video interface, programmable for rising or falling edge.
Horizontal sync for screen video interface, programmable for rising or falling edge.
RISC and system clock input. CPUCLK is used only if SEL_PLL[1:0] = 00.
Pixel clock; two times the actual pixel clock for screen video interface.
2
SAM0417-051701
ESS Technology, Inc.