F49B002UA Datasheet, PDF (9/33 Pages) Elite Semiconductor Memory Technology Inc. – 2 Mbit (256K x 8) 5V Only CMOS Flash Memory

EFST
F49B002UA
Auto-select Command
The auto-select command sequence allows the host
system to access the manufacturer and devices codes,
and determine whether or not a sector is protected.
Table 5 shows the address and data requirements. This
method is an alternative to that shown in Table 3, which
is intended for PROM programmers and requires
V_ID on address bit A9.
The auto-select command sequence is initiated by
writing two unlock cycles, followed by the auto-select
command. The device then enters the auto-select
mode, and the system may read at any address any
number of times, without initiating another command
sequence. The read cycles at address 04H, 08H, 0CH,
and 00H retrieves the EFST manufacturer ID. A read
cycle at address 01H retrieves the device ID. .
7.3 Programming & Erasing Operation Status
The device provides several bits to determine the
status of a programming & Erasing operation: DQ7,
DQ6, Table 6 and the following subsections
describe the functions of these bits. DQ7, and DQ6
each offer a method for determining whether a
program or erase operation is complete or in
progress.
Table 6. Write Operation Status
Operation
Embedded Program Algorithm
Standard
Mode _{Embedded Erase Algorithm}
Sector erase
Chip erase
DQ7
(Note1)
DQ 7
0
0
DQ6
Toggle
Toggle
Toggle
Notes:
1. DQ7 require a valid address when reading status information. Refer to the appropriate subsection for further
details.
DQ7: Data Polling
During a programming operation, DQ7 returns the
complement of the programmed value. During an
erase operation, a “0” is produced on DQ7, with this
switching to a “1” following the operation. On
completion of a programming operation, reading the
device after the rising edge of the last – the sixth -
write enable ( ^WE ) pulse, returns the value just
programmed (“0”) on DQ7.
If ^OE is asserted low before the operation is
completed, the value of DQ7 many change and it may
not represent the correct value. The correct value will
be return on the next read cycle, after the system has
detected that the value has changed from its
complement to the actual value.
Figure 14: Data polling flow chart opposite illustrates
the actual process. Relevant signal pulse timings are
given in Figure 16 : Data polling timing diagram.
DQ6:Toggle BIT I
During program and erase operations, the toggle bit on
DQ6 switches between “0” and “1” on successive bus
read attempts at any address. The toggling can be
detected after the last rising edge of the write enable
___
( WE ) pulse of an erase or program command
sequence and is terminated when the operation is
completed. In the case of programming, the last write
enable pulse is the fourth; for both the sector erase and
chip erase commands, it is the sixth. Figure 15 shows
an example use of this function. Relevant signal pulse
timings are given in Figure 17: Toggle Bit timing
diagram.
Elite Flash Storage Technology Inc.
Publication Date : Sep. 2006
Revision: 1.4
9/33