F49B002UA Datasheet, PDF (1/33 Pages) Elite Semiconductor Memory Technology Inc. – 2 Mbit (256K x 8) 5V Only CMOS Flash Memory

EFST
F49B002UA
2 Mbit (256K x 8)
5V Only CMOS Flash Memory
1. FEATURES
z Single supply voltage 5V ±10%
z Fast access time: 70/90 ns
z Compatible with JEDEC standard
- Pin-out, packages and software commands
compatible with single-power supply Flash
z Low power consumption
- 25mA maximum active current
- 25uA typical standby current 
z 100,000 program/erase cycles typically
z Command register architecture
- Byte programming (10us typical)
- Sector Erase( sector structure: 16KB, 8KB, 8KB,
96KB, 128KB )
z Auto Erase (chip & sector) and Auto Program
- Sector erase and Chip erase.
- Automatically program and verify data at specified
address
z End of program or erase detection
- Data polling
- Toggle bits
z Boot Sector Architecture
- U = Upper Boot Sector
z Packages available:
- 32-pin PDIP
- 32-pin PLCC
2. ORDERING INFORMATION
Part No
F49B002UA-70D
F49B002UA-70N
Boot
Upper
Upper
Speed
70 ns
70 ns
Package
PDIP
PLCC
Part No
F49B002UA-90D
F49B002UA-90N
Boot
Upper
Upper
Speed
90 ns
90 ns
Package
PDIP
PLCC
3. GENERAL DESCRIPTION
The F49B002UA is a 2 Megabit, 5V only CMOS Flash
memory device organized as 256K bytes of 8 bits. This
device is packaged in standard 32-pin PDIP and 32-pin
PLCC. It is designed to be programmed and erased both
in system and can in standard EPROM programmers.
With access times of 70 ns and 90 ns, the F49B002UA
allows the operation of high-speed microprocessors. The
device has separate chip enable _CE, write enable WE ,
and output enable _OE controls. EFST's memory devices
reliably store memory data even after 10,000 program and
erase cycles.
The F49B002UA is entirely pin and command set
compatible with the JEDEC standard for 2 Megabit Flash
memory devices. Commands are written to the command
register using standard microprocessor write timings.
The F49B002UA features a sector erase architecture.
The device memory array is divided into 16 Kbytes, 8K
bytes, 8Kbytes, 96Kbytes, 128Kbytes. Erase capabilities
provide the flexibility to revise the data in the device.
A low V_CC detector inhibits write operations on loss of
power. End of program or erase is detected by the Data
Polling of DQ7, or by the Toggle Bit feature on DQ6. Once
the program or erase cycle has been successfully
completed, the device internally resets to the Read mode.
Elite Flash Storage Technology Inc.
Publication Date : Sep. 2006
Revision: 1.4
1/33