M12S16161A Datasheet, PDF (7/28 Pages) Elite Semiconductor Memory Technology Inc. – 512K x 16Bit x 2Banks Synchronous DRAM

ESMT
M12S16161A
Mode Register
BA A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Address bus
xx
100
LTMODE WT
BL
Burst Read and Single Write (for Write
Through Cache)
00
000
LTMODE WT
BL
Mode Register Set
x =Don’t care
Burst length
A2-A0
000
001
010
011
100
101
110
111
WT=0
1
2
4
8
R
R
R
Full page
WT=1
1
2
4
8
R
R
R
R
Wrap type
0
Sequential
1
Interleave
Mode Register Write Timing
CLOCK
CKE
CS
RAS
CAS
WE
A0-A11
Latency mode
A6-A4
000
001
010
011
100
101
110
111
CAS Latency
R
R
2
3
R
R
R
R
Remark R : Reserved
Mode Register W rite
Elite Semiconductor Memory Technology Inc.
Publication Date : Jun. 2005
Revision : 1.0
7/28