M12S16161A Datasheet, PDF (18/28 Pages) Elite Semiconductor Memory Technology Inc. – 512K x 16Bit x 2Banks Synchronous DRAM

ESMT
Read & Write Cycle at Different Bank @ Burst Length = 4
M12S16161A
*Note: 1.tCDL should be met to complete write.
Elite Semiconductor Memory Technology Inc.
Publication Date : Jun. 2005
Revision : 1.0
18/28