M12S16161A Datasheet, PDF (5/28 Pages) Elite Semiconductor Memory Technology Inc. – 512K x 16Bit x 2Banks Synchronous DRAM

ESMT
AC OPERATING TEST CONDITIONS (VDD=2.5V ± 0.2V,TA= 0 °C ~ 70 °C )
Parameter
Input levels (Vih/Vil)
Input timing measurement reference level
Input rise and fall time
Output timing measurement reference level
Output load condition
Value
0.9 x VDDQ / 0.2
0.5 x VDDQ
tr / tf = 1 / 1
0.5 x VDDQ
See Fig.2
VDDQ
Output
500
500
VOH(DC) = VDDQ-0.2V, IOH = -0.1mA
VOL(DC) = 0.2V, IOL = 0.1mA
30 pF
Output
Z0=50
M12S16161A
Unit
V
V
ns
V
Vtt =0.5x VDDQ
50
20 pF
(Fig.1) DC Output Load circuit
OPERATING AC PARAMETER
(AC operating conditions unless otherwise noted)
Parameter
Symbol
Row active to row active delay
RAS to CAS delay
Row precharge time
Row active time
Row cycle time
Last data in to new col. Address delay
Last data in to row precharge
Last data in to burst stop
Col. Address to col. Address delay
Number of valid output data
tRRD(min)
tRCD(min)
tRP(min)
tRAS(min)
tRAS(max)
tRC(min)
tCDL(min)
tRDL(min)
tBDL(min)
tCCD(min)
CAS latency=3
CAS latency=2
CAS latency=1
(Fig.2) AC Output Load Circuit
Version
-10
-15
20
30
30
30
20
30
50
60
100
70
90
1
2
1
1
2
1
0
Unit
Note
ns
1
ns
1
ns
1
ns
1
us
ns
1
CLK
2
CLK
2
CLK
2
CLK
3
ea
4
Note: 1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time and
then rounding off to the next higher integer.
2. Minimum delay is required to complete write.
3. All parts allow every cycle column address change.
4. In case of row precharge interrupt, auto precharge and read burst stop.
The earliest a precharge command can be issued after a Read command without the loss of data is CL+BL-2 clocks.
Elite Semiconductor Memory Technology Inc.
Publication Date : Jun. 2005
Revision : 1.0
5/28