M13S256328A Datasheet, PDF (6/47 Pages) Elite Semiconductor Memory Technology Inc. – 2M x 32 Bit x 4 Banks Double Data Rate SDRAM

ESMT
AC Operating Test Conditions
Parameter
Input reference voltage for clock (V_REF)
Input signal maximum peak swing
Input signal minimum slew rate
Input levels (V_IH/V_IL)
Input timing measurement reference level
Output timing reference level
M13S256328A
Value
0.5*V_DDQ
1.5
1.0
V_REF+0.35/V_REF-0.35
V_REF
V_TT
Unit
V
V
V/ns
V
V
V
AC Timing Parameter & Specifications
(V_DD = 2.3V~2.7V, V_DDQ=2.3V~2.7V, T_A =0 °C to 70 °C )(Note)
Parameter
Symbol
-5
min
max
Clock Period
CL2
7.5
15
CL2.5
t_CK
5.0
10
ns
CL3
5.0
10
Access time from CLK/ CLK
t_AC
-0.65
+0.65
ns
CLK high-level width
t_CH
0.45
0.55
t_CK
CLK low-level width
t_CL
0.45
0.55
t_CK
Data strobe edge to clock edge
t_DQSCK
-0.65
+0.65
ns
Clock to first rising edge of DQS delay t_DQSS
0.85
1.15
t_CK
Data-in and DM setup time (to DQS)
t_DS
0.5
-
ns
Data-in and DM hold time (to DQS)
t_DH
0.5
-
ns
DQ and DM input pulse width (for each input)
t_DIPW
1.75
-
ns
Input setup time
t_IS
1.0
-
ns
Input hold time
t_IH
1.0
-
ns
Control and Address input pulse width
t_IPW
2.2
-
ns
DQS input high pulse width
t_DQSH
0.4
0.6
t_CK
DQS input low pulse width
t_DQSL
0.4
0.6
t_CK
DQS falling edge to CLK rising-setup time
t_DSS
0.2
-
t_CK
DQS falling edge from CLK rising-hold time
t_DSH
0.2
-
t_CK
Data strobe edge to output data edge
t_DQSQ
-
0.4
ns
Data-out high-impedance window from
CLK/ CLK
tHZ
-
+0.7
ns
Data-out low-impedance window from
tLZ
-0.7
+0.7
ns
CLK/ CLK
Elite Semiconductor Memory Technology Inc.
Publication Date : May. 2007
Revision : 1.2
6/47