M13S256328A Datasheet, PDF (4/47 Pages) Elite Semiconductor Memory Technology Inc. – 2M x 32 Bit x 4 Banks Double Data Rate SDRAM

ESMT
DC Operation Condition & Specifications
M13S256328A
DC Operation Condition
Recommended operating conditions (Voltage reference to V_SS = 0V, T_A = 0 to 70 °C )
Parameter
Supply voltage
I/O Supply voltage
I/O Reference voltage
I/O Termination voltage (system)
Input logic high voltage
Input logic low voltage
Input leakage current
Output leakage current
Output High Current (Normal strength driver)
(V_OUT =V_DDQ-0.373V, min V_REF, min V_TT)
Output Low Current (Normal strength driver)
(V_OUT = 0.373V)
Output High Current (Weak strength driver)
(V_OUT =V_DDQ-0.763V, min V_REF, min V_TT)
Output Low Current (Weak strength driver)
(V_OUT = 0.763V)
Symbol
V_DD
V_DDQ
V_REF
V_TT
V_IH (DC)
V_IL (DC)
I_I
I_OZ
I_OH
Min
2.3
2.3
0.49*V_DDQ
V_REF - 0.04
V_REF + 0.15
-0.3
-5
Max
2.7
2.7
0.51*V_DDQ
V_REF + 0.04
V_DDQ + 0.3
V_REF - 0.15
5
-5
5
-16.8
I_OL
+16.8
I_OH
-9
I_OL
+9
Unit
V
V
V
V
V
V
μA
μA
mA
mA
mA
mA
Note
1
2
3
Notes 1. V_REF is expected to be equal to 0.5* V_DDQ of the transmitting device, and to track variations in the DC level of the
same. Peak-to-peak noise on V_REF may not exceed 2% of the DC value.
2. V_TT is not applied directly to the device. V_TT is system supply for signal termination resistors, is expected to be set
equal to V_REF, and must track variations in the DC level of V_REF .
Elite Semiconductor Memory Technology Inc.
Publication Date : May. 2007
Revision : 1.2
4/47