M13S256328A Datasheet, PDF (3/47 Pages) Elite Semiconductor Memory Technology Inc. – 2M x 32 Bit x 4 Banks Double Data Rate SDRAM

ESMT
M13S256328A
Pin Description
(M13S256328A)
Pin Name
A0~A11,
BA0,BA1
Function
Address inputs
- Row address A0~A11
- Column address A0~A7, A9
A8/AP : AUTO Precharge
BA0, BA1 : Bank selects (4 Banks)
DQ0~DQ31 Data-in/Data-out
RAS
CAS
WE
V_SS
V_DD
DQS0~DQS3
(for FBGA)
Row address strobe
Column address strobe
Write enable
Ground
Power
Bi- directional Data Strobe.
DQS0 correspond to the data on DQ0~DQ7.
DQS1 correspond to the data on DQ8~DQ15.
DQS2 correspond to the data on DQ16~DQ23.
DQS3 correspond to the data on DQ24~DQ31.
Pin Name
Function
DM0~DM3 DQ Mask enable in write cycle.
CLK, CLK
CKE
CS
V_DDQ
V_SSQ
V_REF
Clock input
Clock enable
Chip select
Supply Voltage for GDQ
Ground for DQ
Reference Voltage for SSTL
NC
No connection
Absolute Maximum Rating
Parameter
Voltage on any pin relative to V_SS
Voltage on V_DD supply relative to V_SS
Voltage on V_DDQ supply relative to V_SS
Storage temperature
Power dissipation
Short circuit current
Symbol
V_IN, V_OUT
V_DD, V_DDQ
V_DDQ
T_STG
P_D
I_OS
Value
-0.5 ~ 3.6
-1.0 ~ 3.6
-0.5 ~ 3.6
-55 ~ +150
TBD
50
Unit
V
V
V
°C
W
mA
Note : Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded.
Functional operation should be restricted to recommend operation condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
Elite Semiconductor Memory Technology Inc.
Publication Date : May. 2007
Revision : 1.2
3/47