M12L32321A Datasheet, PDF (6/28 Pages) Elite Semiconductor Memory Technology Inc. – 512K x 32Bit x 2Banks Synchronous DRAM

ESMT
M12L32321A
AC CHARACTERISTICS (AC operating conditions unless otherwise noted)
Parameter
-5.5
-6
-7
Symbol _{Min Max Min Max Min Max}
Unit
Note
CAS Latency =3
5.5
6
7
CLK cycle time
tCC
1000
1000
1000
ns
1
CAS Latency =2
10
10
10
CLK to valid
output delay
CAS Latency =3
tSAC
CAS Latency =2
-
6
-
6
-
-
6
6
-
-
6
6
ns
1
Output data hold time
tOH
2.5 -
2.5
-
2.5
-
ns
2
CLK high pulse width
tCH
2
-
2
-
2.5
-
ns
3
CLK low pulse width
tCL
2
-
2
-
2.5
-
ns
3
Input setup time
tSS
1.8 -
2
-
2
-
ns
3
Input hold time
tSH
1.2 -
2
-
2
-
ns
3
CLK to output in Low-Z
tSLZ
0
-
0
-
0
-
ns
2
CLK to output in ^{CAS Latency =3}
Hi-Z
CAS Latency =2
tSHZ
-
6
-
-
6
-
6
6
-
-
6
6
ns
-
*All AC parameters are measured from half to half.
Note: 1.Parameters depend on programmed CAS latency.
2.If clock rising time is longer than 1ns,(tr/2-0.5)ns should be added to the parameter.
3.Assumed input rise and fall time (tr & tf)=1ns.
If tr & tf is longer than 1ns, transient time compensation should be considered, i.e., [(tr+ tf)/2-1]ns should be added to the
parameter.
Parameter
CLK to valid
output delay
CAS Latency =3
CAS Latency =2
Output data hold time
CLK to output in ^{CAS Latency =3}
Hi-Z
CAS Latency =2
Symbol
tSAC
tOH
tSHZ
-5.5
Min
Max
-
5.5
-
5.5
2
-
-
5.5
-
5.5
Note: 4. Special condition (Output Load ≤ 10 ohm+10 pF)
-6
Min
Max
-
5.5
-
5.5
2
-
-
5.5
-
5.5
Unit Note
ns
4
ns
4
ns
4
Elite Semiconductor Memory Technology Inc.
Publication Date : Oct. 2008
Revision : 1.1
6/28