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M12L32321A Datasheet, PDF (4/28 Pages) Elite Semiconductor Memory Technology Inc. – 512K x 32Bit x 2Banks Synchronous DRAM | |||
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ESMT
M12L32321A
DC CHARACTERISTICS
(Recommended operating condition unless otherwise noted, TA = 0 to 70 °C VIH(min)/VIL(max)=2.0V/0.8V)
Parameter
Symbol
Test Condition
CAS
Version
Latency -5.5
-6
-7
Operating Current
(One Bank Active)
ICC1
Burst Length = 1
tRC ⥠tRC (min), tCC ⥠tCC (min), IOL= 0mA
160
140
120
Precharge Standby
ICC2P
CKE ⤠VIL(max), tCC =15ns
2
Current in power-down
mode
ICC2PS CKE ⤠VIL(max), CLK ⤠VIL(max), tCC = â
2
Precharge Standby
ICC2N
CKE ⥠VIH(min), CS ⥠VIH(min), tCC =15ns
25
Current in non
Input signals are changed one time during 30ns
power-down mode
ICC2NS
CKE ⥠VIH(min), CLK ⤠VIL(max), tCC = â
Input signals are stable
15
Active Standby Current ICC3P
CKE ⤠VIL(max), tCC =15ns
10
in power-down mode
ICC3PS CKE ⤠VIL(max), CLK ⤠VIL(max), tCC = â
10
Active Standby Current ICC3N
in non power-down
CKE ⥠VIH(min), CS ⥠VIH(min), tCC=15ns
Input signals are changed one time during 2clks
25
mode
All other pins ⥠VDD-0.2V or ⤠0.2V
(One Bank Active)
ICC3NS
CKE ⥠VIH (min), CLK ⤠VIL(max), tCC= â
Input signals are stable
15
Operating Current
(Burst Mode)
IOL= 0Ma, Page Burst
ICC4
All Band Activated, tCCD = tCCD (min)
3
160
140
120
2
160
140
120
Refresh Current
ICC5
tRC ⥠tRC(min)
160
140
120
Self Refresh Current
ICC6
CKE ⤠0.2V
1
Note: 1.Measured with outputs open. Addresses are changed only one time during tCC(min).
2.Refresh period is 64ms. Addresses are changed only one time during tCC(min).
Unit Note
mA 1
mA -
mA -
mA -
mA -
mA -
mA
-
mA -
mA 1
mA 1
mA 2
mA -
Elite Semiconductor Memory Technology Inc.
Publication Date : Oct. 2008
Revision : 1.1
4/28
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