M12L32321A Datasheet, PDF (2/28 Pages) Elite Semiconductor Memory Technology Inc. – 512K x 32Bit x 2Banks Synchronous DRAM

ESMT
M12L32321A
CLK
CKE
Clock
Generator
Address
CS
RAS
CAS
WE
FUNCTIONAL BLOCK DIAGRAM
Mode
Register
Row
Address
Buffer
&
Refresh
Counter
Column
Address
Buffer
&
Refresh
Counter
Bank B
Bank A
Sense Amplifier
Column Decoder
Data Control Circuit
DQM0~3
DQ
PIN FUNCTION DESCRIPTION
Pin
CLK
Name
System Clock
CS
Chip Select
CKE
Clock Enable
A0 ~ A10
BA
RAS
Address
Bank Select Address
Row Address Strobe
CAS
Column Address Strobe
WE
DQM0~3
Write Enable
Data Input / Output Mask
Input Function
Active on the positive going edge to sample all inputs.
Disables or enables device operation by masking or enabling all inputs except
CLK, CKE and DQM.
Masks system clock to freeze operation from the next clock cycle.
CKE should be enabled at least one cycle prior to new command.
Disable input buffers for power down in standby.
Row / column addresses are multiplexed on the same pins.
Row address : RA0 ~ RA10, column address : CA0 ~ CA7
Selects bank to be activated during row address latch time.
Selects bank for read/write during column address latch time.
Latches row addresses on the positive going edge of the CLK with RAS low.
Enables row access & precharge.
Latches column addresses on the positive going edge of the CLK with
CAS low.
Enables column access.
Enables write operation and row precharge.
Latches data in starting from CAS , WE active.
Makes data output Hi-Z, tSHZ after the clock and masks the output.
Blocks data input when DQM active.
Elite Semiconductor Memory Technology Inc.
Publication Date : Oct. 2008
Revision : 1.1
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