M12L128324A-2M Datasheet, PDF (6/44 Pages) Elite Semiconductor Memory Technology Inc. – JEDEC standard 3.3V power supply

ESMT
M12L128324A (2M)
Parameter
Symbol
Col. address to col. address delay tCCD(min)
Number of valid
Output data
CAS latency = 3
CAS latency = 2
CAS latency = 1
Version
-6
-7
1
2
1
0
Unit
Note
CLK
3
ea
4
Note: 1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time and then
rounding off to the next higher integer.
2. Minimum delay is required to complete write.
3. All parts allow every cycle column address change.
4. In case of row precharge interrupt, auto precharge and read burst stop.
5. A new command may be given t_RFC after self refresh exit.
AC CHARACTERISTICS (AC operating condition unless otherwise noted)
Parameter
Symbol
CAS latency = 3
CLK cycle time
CAS latency = 2
tCC
CAS latency = 1
CLK to valid
output delay
CAS latency = 3
CAS latency = 2
tSAC
CAS latency = 1
Output data
hold time
CAS latency = 3
CAS latency = 2
tOH
CAS latency = 1
CLK high pulse width
tCH
CLK low pulse width
tCL
Input setup time
tSS
Input hold time
tSH
CLK to output in Low-Z
tSLZ
CLK to output
in Hi-Z
CAS latency = 3
CAS latency = 2
tSHZ
CAS latency = 1
-6
Min
Max
6
10
1000
20
-
5.5
-
6
-
17
2
-
2
-
2
-
2
-
2
-
2
-
1
-
1
-
-
5.5
-
6
-
17
-7
Min
7
8.6
20
-
-
-
2
2
2
2.5
2.5
2
1
1
-
-
-
Max
1000
6
6
18
-
-
-
-
-
-
-
-
6
6
18
Note:
1. Parameters depend on programmed CAS latency.
2. If clock rising time is longer than 1ns. (tr/2 - 0.5) ns should be considered.
3. Assumed input rise and fall time (tr & tf) =1ns.
If tr & tf is longer than 1ns transient time compensation should be considered.
i.e., [(tr + tf)/2 – 1] ns should be added to the parameter.
Unit Note
ns
1
ns
1,2
ns
2
ns
3
ns
3
ns
3
ns
3
ns
2
ns
-
Elite Semiconductor Memory Technology Inc.
Publication Date: Mar. 2011
Revision: 1.2
6/44