M12L128324A-2M Datasheet, PDF (30/44 Pages) Elite Semiconductor Memory Technology Inc. – JEDEC standard 3.3V power supply

ESMT
Read & Write Cycle at Same Bank @ Burst Length = 4
M12L128324A (2M)
*Note:
1. Minimum row cycle times is required to complete internal DRAM operation.
2. Row precharge can interrupt burst on any cycle. [CAS Latency-1] number of valid output data is available after Row
precharge. Last valid output will be Hi-Z (tSHZ) after the clock.
3. Output will be Hi-Z after the end of burst. (1, 2, 4, 8 & Full page bit burst)
Elite Semiconductor Memory Technology Inc.
Publication Date: Mar. 2011
Revision: 1.2
30/44