M12L128324A-2M Datasheet, PDF (2/44 Pages) Elite Semiconductor Memory Technology Inc. – JEDEC standard 3.3V power supply

ESMT
BLOCK DIAGRAM
CLK
CKE
Clock
Generator
Address
CS
RAS
CAS
WE
Mode
Register
Row
Address
Buffer
&
Refresh
Counter
Column
Address
Buffer
&
Refresh
Counter
M12L128324A (2M)
Bank D
Bank C
Bank B
Bank A
Sense Amplifier
Column Decoder
Data Control Circuit
DQM0~3
DQ
PIN DESCRIPTION
PIN
CLK
CS
CKE
A0 ~ A11
BA0 , BA1
RAS
NAME
System Clock
Chip Select
Clock Enable
Address
Bank Select Address
INPUT FUNCTION
Active on the positive going edge to sample all inputs
Disables or enables device operation by masking or enabling all inputs except
CLK, CKE and DQM0-3.
Masks system clock to freeze operation from the next clock cycle.
CKE should be enabled at least one cycle prior new command.
Disable input buffers for power down in standby.
Row / column address are multiplexed on the same pins.
Row address : RA0~RA11, column address : CA0~CA7
Selects bank to be activated during row address latch time.
Selects bank for read / write during column address latch time.
Row Address Strobe Latches row addresses on the positive going edge of the CLK with RAS low.
Enables row access & precharge.
CAS
WE
DQM0~3
DQ0 ~ DQ31
V_DD / V_SS
V_DDQ / V_SSQ
N.C
Column Address
Strobe
Write Enable
Data Input / Output
Mask
Data Input / Output
Power Supply /
Ground
Data Output Power /
Ground
No Connection
Latches column address on the positive going edge of the CLK with CAS low.
Enables column access.
Enables write operation and row precharge.
Latches data in starting from CAS , WE active.
Makes data output Hi-Z, t_SHZ after the clock and masks the output.
Blocks data input when DQM active.
Data inputs / outputs are multiplexed on the same pins.
Power and ground for the input buffers and the core logic.
Isolated power supply and ground for the output buffers to provide improved
noise immunity.
This pin is recommended to be left No Connection on the device.
Elite Semiconductor Memory Technology Inc.
Publication Date: Mar. 2011
Revision: 1.2
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