M12L32321A-2G Datasheet, PDF (5/28 Pages) Elite Semiconductor Memory Technology Inc. – JEDEC standard 3.3V ± 0.3V power supply

ESMT
AC OPERATING TEST CONDITIONS (V_DD=3.3V  0.3V)
Parameter
Input levels (Vih/Vil)
Input timing measurement reference level
Input rise and fall time
Output timing measurement reference level
Output load condition
Value
2.4 / 0.4
1.4
tr / tf = 1 / 1
1.4
See Fig.2
M12L32321A (2G)
Unit
V
V
ns
V
OPERATING AC PARAMETER
(AC operating conditions unless otherwise noted)
Parameter
Row active to row active delay
Symbol
tRRD(min)
Version
Unit Note
-5
-6
-7
10
12
14
ns
1
RAS to CAS delay
tRCD(min)
15
18
21
ns
1
Row precharge time
tRP(min)
15
18
21
ns
1
Row active time
tRAS(min)
40
42
42
ns
1
tRAS(max)
100
us
-
@ Operating
tRC(min)
55
60
63
ns
1
Row cycle time
@ Auto refresh
tRFC(min)
55
60
63
ns
1, 5
Last data in to new col. Address delay
tCDL(min)
1
CLK
2
Last data in to row precharge
tRDL(min)
2
CLK
2
Last data in to burst stop
tBDL(min)
1
CLK
2
Col. Address to col. Address delay
tCCD(min)
1
CLK
3
Refresh period (4,096 rows)
tREF(max)
64
ms
6
Number of valid output data
CAS latency=3
2
CAS latency=2
1
ea
4
Note: 1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time and
then rounding off to the next higher integer.
2. Minimum delay is required to complete write.
3. All parts allow every cycle column address change.
4. In case of row precharge interrupt, auto precharge and read burst stop.
The earliest a precharge command can be issued after a Read command without the loss of data is CL+BL-2 clocks.
5. A new command may be given tRFC after self refresh exit.
6. A maximum of eight consecutive AUTO REFRESH commands (with t_RFC(min)) can be posted to any given SDRAM, and
the maximum absolute interval between any AUTO REFRESH command and the next AUTO REFRESH command is
8x15.6 μ s.
Elite Semiconductor Memory Technology Inc.
Publication Date : Jul. 2012
Revision : 1.0
5/28