M12L32321A-2G Datasheet, PDF (1/28 Pages) Elite Semiconductor Memory Technology Inc. – JEDEC standard 3.3V ± 0.3V power supply

ESMT
SDRAM
M12L32321A (2G)
512K x 32Bit x 2Banks
Synchronous DRAM
FEATURES
 JEDEC standard 3.3V ± 0.3V power supply
 LVTTL compatible with multiplexed address
 Dual banks operation
 MRS cycle with address key programs
- CAS Latency (2 & 3 )
- Burst Length (1, 2, 4, 8 & full page)
- Burst Type (Sequential & Interleave)
 All inputs are sampled at the positive going edge of the
system clock
 Burst Read Single-bit Write operation
 DQM for masking
 Auto & self refresh
 64ms refresh period (4K cycle)
GENERAL DESCRIPTION
The M12L32321A is 33,554,432 bits synchronous high data
rate Dynamic RAM organized as 2 x 524,288 words by 32
bits, fabricated with high performance CMOS technology.
Synchronous design allows precise cycle control with the use
of system clock I/O transactions are possible on every clock
cycle. Range of operating frequencies, programmable burst
length and programmable latencies allow the same device to
be useful for a variety of high bandwidth, high performance
memory system applications.
ORDERING INFORMATION
Product ID
M12L32321A-5BG2G
M12L32321A-6BG2G
M12L32321A-7BG2G
Max Freq.
200MHz
166MHz
143MHz
Package
90 FBGA
90 FBGA
90 FBGA
Comments
Pb-free
Pb-free
Pb-free
BALL CONFIGURATION (TOP VIEW)
(BGA90, 8mmX13mmX1mm Body, 0.8mm Ball Pitch)
1
2
3
456
7
8
9
A DQ26 DQ24 VSS
VDD DQ23 DQ21
B DQ28 VDDQ VSSQ
VDDQ VSSQ DQ19
C VSSQ DQ27 DQ25
DQ22 DQ20 VDDQ
D VSSQ DQ29 DQ30
DQ17 DQ18 VDDQ
E VDDQ DQ31 NC
NC DQ16 VSSQ
F VSS DQM3 A3
A2 DQM2 VDD
G A4 A5 A6
A10/AP A0 A1
H A7 A8 NC
NC NC NC
J CLK CKE A9
BA CS RAS
K DQM1 NC NC
CAS WE DQM0
L VDDQ DQ8 VSS
VDD DQ7 VSSQ
M VSSQ DQ10 DQ9
DQ6 DQ5 VDDQ
N VSSQ DQ12 DQ14
DQ1 DQ3 VDDQ
P DQ11 VDDQ VSSQ
VDDQ VSSQ DQ4
R DQ13 DQ15 VSS
VDD DQ0 DQ2
Elite Semiconductor Memory Technology Inc.
Publication Date : Jul. 2012
Revision : 1.0
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