M12L32162A Datasheet, PDF (5/29 Pages) Elite Semiconductor Memory Technology Inc. – 1M x 16Bit x 2Banks Synchronous DRAM

ESMT
Preliminary
M12L32162A
DC CHARACTERISTICS
(Recommended operating condition unless otherwise noted, TA = 0 to 70 °C VIH(min)/VIL(max)=2.0V/0.8V)
Parameter
Symbol
Test Condition
CAS
Latency
Version
-7
Operating Current
(One Bank Active)
ICC1
Burst Length = 1
tRC ≥ tRC (min), tCC ≥ tCC (min), IOL= 0mA
100
Precharge Standby
ICC2P
CKE ≤ VIL(max), tCC =15ns
2
Current in power-down
mode
ICC2PS CKE ≤ VIL(max), CLK ≤ VIL(max), tCC = ∞
2
Precharge Standby
ICC2N
CKE ≥ VIH(min), CS ≥ VIH(min), tCC =15ns
25
Current in non
Input signals are changed one time during 30ns
power-down mode
ICC2NS
CKE ≥ VIH(min), CLK ≤ VIL(max), tCC = ∞
Input signals are stable
15
Active Standby Current ^ICC3P
CKE ≤ VIL(max), tCC =15ns
10
in power-down mode
ICC3PS CKE ≤ VIL(max), CLK ≤ VIL(max), tCC = ∞
10
Active Standby Current ICC3N
in non power-down
CKE ≥ VIH(min), CS ≥ VIH(min), tCC=15ns
Input signals are changed one time during 30ns
25
mode
(One Bank Active)
ICC3NS
CKE ≥ VIH (min), CLK ≤ VIL(max), tCC= ∞
Input signals are stable
15
Operating Current
(Burst Mode)
IOL= 0Ma, Page Burst
ICC4
All Band Activated, tCCD = tCCD (min)
3
2
120
120
Refresh Current
ICC5
tRC ≥ tRC(min)
120
Self Refresh Current
ICC6
CKE ≤ 0.2V
1
Note: 1.Measured with outputs open. Addresses are changed only one time during tCC(min).
2.Refresh period is 64ms. Addresses are changed only one time during tCC(min).
Unit Note
mA 1
mA
mA
mA
mA
mA
mA
mA 1
mA 2
mA
Elite Semiconductor Memory Technology Inc.
Publication Date : Apr. 2007
Revision : 0.3
5/29