M12L32162A Datasheet, PDF (27/29 Pages) Elite Semiconductor Memory Technology Inc. – 1M x 16Bit x 2Banks Synchronous DRAM

ESMT
Preliminary
PACKING DIMENSIONS
54-LEAD TSOP(II) SDRAM (400mil) (1:3)
M12L32162A
D
54
PIN1
IDENTIFIER
1
-C-
e
b
SEATING PLANE
-H-
SEE
DETAIL A
A
28
A2
0.21 REF
E1 E
A1
-C-
0.665 REF
27
-C-
B
O
B
L
L1
DETAIL "A"
b
c c1
0.10
b1
SECTION B-B
Symbol
A
A1
A2
b
b1
c
c1
D
E
E1
L
L1
e
Θ
Dimension in mm
Min Norm Max
1.20
0.05 0.10 0.15
0.95 1.00 1.05
0.25
0.45
0.25 0.35 0.40
0.12
0.21
0.10 0.127 0.16
22.22 BSC
11.76 BSC
10.16 BSC
0.40 0.50 0.60
0.80 REF
0.80 BSC
0°
10°
Dimension in inch
Min Norm Max
0.047
0.002 0.004 0.006
0.037 0.039 0.041
0.010
0.018
0.010 0.014 0.016
0.005
0.008
0.004 0.005 0.006
0.875 BSC
0.463 BSC
0.400 BSC
0.016 0.020 0.024
0.031 REF
0.031 BSC
0°
10°
Elite Semiconductor Memory Technology Inc.
Publication Date : Apr. 2007
Revision : 0.3
27/29