M53D256328A-2F Datasheet, PDF (30/47 Pages) Elite Semiconductor Memory Technology Inc. – Internal pipelined double-data-rate architecture, two data

ESMT
M53D256328A (2F)
Basic Timing (Setup, Hold and Access Time @ BL=4, CL=3)
0
1
CLK
CLK
CKE
tCH tCL
tCK
2
3
4
5
HIGH
6
7
8
9
10
11
12
13
CS
RAS
tIS
tIH
CAS
BA0, BA1
BAa
A10/AP
Ra
ADDR
(A0~An)
Ra
WE
DQS
DQ
DM
BAa
Ca
Hi-Z
Hi-Z
tDQSS
BAb
tDQSS
tRPRE
tDQSCK
tLZ
tAC
tQH
Qa0
tRPST
tDQSQ
tHZ
Qa1 Qa2 Qa3
tQHS
Cb
Hi-Z
Hi-Z
tDQSS
tDSH tDSS
tDQSL
tWPST
tWPRES
tDQSH
tWPRE
Db0 Db1 Db2 Db3
tDS tDH
Hi-Z
Hi-Z
COMMAND
Active
READ
WRITE
10122B32R.B
Note: tHP is lesser of tCL or tCH clock transition collectively when a bank is active.
Elite Semiconductor Memory Technology Inc.
Publication Date :Feb. 2014
Revision : 1.0
30/47