M53D256328A-2F Datasheet, PDF (1/47 Pages) Elite Semiconductor Memory Technology Inc. – Internal pipelined double-data-rate architecture, two data

ESMT
Mobile DDR SDRAM
Features
 JEDEC Standard
 Internal pipelined double-data-rate architecture, two data
access per clock cycle
 Bi-directional data strobe (DQS)
 No DLL; CLK to DQS is not synchronized.
 Differential clock inputs (CLK and CLK )
 Four bank operation
 CAS Latency : 3
 Burst Type : Sequential and Interleave
 Burst Length : 2, 4, 8, 16
 Special function support
- PASR (Partial Array Self Refresh)
- Internal TCSR (Temperature Compensated Self
Refresh)
- DS (Drive Strength)
M53D256328A (2F)
2M x 32 Bit x 4 Banks
Mobile DDR SDRAM
 All inputs except data & DM are sampled at the rising
edge of the system clock(CLK)
 DQS is edge-aligned with data for READ; center-aligned
with data for WRITE
 Data mask (DM) for write masking only
 V_DD/V_DDQ = 1.7V ~ 1.95V
 Auto & Self refresh
 15.6us refresh interval (64ms refresh period, 4K cycle)
 LVCMOS-compatible inputs
Ordering Information
Product ID
M53D256328A -5BG2F
M53D256328A -6BG2F
M53D256328A -7.5BG2F
Max Freq.
200MHz
166MHz
133MHz
V_DD
Package
Comments
1.8V 144 ball FBGA Pb-free
Functional Block Diagram
CLK
CLK
CKE
Clock
Generator
Address
Mode Register &
Extended Mode
Register
Row
Address
Buffer
&
Refresh
Counter
CS
RAS
CAS
WE
Column
Address
Buffer
&
Refresh
Counter
Bank D
Bank C
Bank B
Bank A
Sense Amplifier
Column Decoder
Data Control Circuit
DQS
DM
DQ
Elite Semiconductor Memory Technology Inc.
Publication Date :Feb. 2014
Revision : 1.0
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