M53D2561616A-2F Datasheet, PDF (27/47 Pages) Elite Semiconductor Memory Technology Inc. – Bi-directional data strobe (DQS)

ESMT
M53D2561616A (2F)
Power Down
Power down is entered when CKE is registered Low (no accesses can be in progress). If power down occurs when all banks are
idle, this mode is referred to as precharge power-down; if power down occurs when there is a row active in any bank, this mode is
referred to as active power-down.
Entering power down deactivates the input and output buffers, excluding CLK, CLK and CKE. In power down mode, CKE Low
must be maintained, and all other input signals are “Don’t Care”. The minimum power down duration is specified by t_CKE. However,
power down duration is limited by the refresh requirements of the device.
The power down state is synchronously exited when CKE is registered High (along with a NOP or DESELECT command). A valid
command may be applied t_XP after exit from power down.
CLK
CLK
CKE
tRP
tIS
tCKE
C O M M A N D Precharge
Enter Precharge
power-down
mode
tXP
tIS
tIS
Active
tCKE
Exit Precharge
power-down
mode
Enter Active
power-down
mode
tXP
tIS
Read
Exit Active
power-down
mode
Functional Truth Table
Truth Table – CKE ^{[Note 1~10]}
CKE n-1 CKE n
Current State
COMMAND n
ACTION n
NOTE
L
L
Power Down
X
Maintain Power Down
L
L
Self Refresh
X
Maintain Self Refresh
L
L
Deep Power Down
X
Maintain Deep Power Down
L
H
Power Down
NOP or DESELECT
Exit Power Down
5,6,9
L
H
Self Refresh
NOP or DESELECT
Exit Self Refresh
5,7,10
L
H
Deep Power Down
NOP or DESELECT
Exit Deep Power Down
5,8
H
L
All Banks Idle
NOP or DESELECT
Precharge Power Down Entry
5
H
L
Bank(s) Active
NOP or DESELECT
Active Power Down Entry
5
H
L
All Banks Idle
AUTO REFRESH
Self Refresh Entry
H
L
All Banks Idle
BURST TERMINATE
Enter Deep Power Down
H
H
See the other Truth Tables
Notes:
1. CKE n is the logic state of CKE at clock edge n; CKE n-1 was the state of CKE at the previous clock edge.
2. Current state is the state of Mobile DDR immediately prior to clock edge n.
3. COMMAND n is the command registered at clock edge n, and ACTION n is the result of COMMAND n.
4. All states and sequences not shown are illegal or reserved.
5. DESELECT and NOP are functionally interchangeable.
6. Power Down exit time (t_XP) should elapse before a command other than NOP or DESELECT is issued.
7. SELF REFRESH exit time (t_XSR) should elapse before a command other than NOP or DESELECT is issued.
8. The Deep Power Down exit procedure must be followed the figure of Deep Power Down Mode Entry & Exit Cycle.
9. The clock must toggle at least once during the t_XP period.
10. The clock must toggle at least once during the t_XSR time.
Elite Semiconductor Memory Technology Inc.
Publication Date : Feb. 2014
Revision : 1.1
27/47