F25L32QA Datasheet, PDF (20/42 Pages) Elite Semiconductor Memory Technology Inc. – 3V Only 32 Mbit Serial Flash Memory with Dual and Quad

ESMT
(Preliminary)
F25L32QA
Page Program (PP)
The Page Program instruction allows many bytes to be
programmed in the memory. The bytes must be in the erased
state (FFH) when initiating a Program operation. A Page
Program instruction applied to a protected memory area will be
ignored.
Prior to any Write operation, the Write Enable (WREN) instruction
must be executed. CE must remain active low for the duration
of the Page Program instruction. The Page Program instruction is
initiated by executing an 8-bit command, 02H, followed by
address bits [A₂₃-A₀]. Following the address, at least one byte
Data is input (the maximum of input data can be up to 256 bytes).
If the 8 least significant address bits [A₇-A₀] are not all zero, all
transmitted data that goes beyond the end of the current page
are programmed from the start address of the same page (from
the address whose 8 least significant bits [A₇-A₀] are all zero).
If more than 256 bytes Data are sent to the device, previously
latched data are discarded and the last 256 bytes Data are
guaranteed to be programmed correctly within the same page. If
less than 256 bytes Data are sent to device, they are correctly
programmed at the requested addresses without having any
effects on the other bytes of the same page.
CE must be driven high before the instruction is executed. The
user may poll the BUSY bit in the software status register or wait
T_PP for the completion of the internal self-timed Page Program
operation. While the Page Program cycle is in progress, the Read
Status Register instruction may still be accessed for checking the
status of the BUSY bit. It is recommended to wait for a duration of
T_BP1 before reading the status register to check the BUSY bit.
The BUSY bit is a 1 during the Page Program cycle and becomes
a 0 when the cycle is finished and the device is ready to accept
other instructions again. After the Page Program cycle has
finished, the Write-Enable-Latch (WEL) bit in the Status Register
is cleared to 0. See Figure 10 for the Page Program sequence.
Figure 10: Page Program Sequence
Elite Semiconductor Memory Technology Inc.
Publication Date: Jan. 2009
Revision: 0.2
20/42