F25L32QA Datasheet, PDF (18/42 Pages) Elite Semiconductor Memory Technology Inc. – 3V Only 32 Mbit Serial Flash Memory with Dual and Quad

ESMT
(Preliminary)
F25L32QA
Fast Read Quad Output (50 MHz ~ 100 MHz)
The Fast Read Quad Output (6B) instruction is similar to the Fast
Read Dual Output (3BH) instruction except the data is output on
bidirectional I/O pins (SIO0, SIO1, SIO2 and SIO3). A Quad
Enable (QE) bit of Status Register-2 must be set “1” to enable
Quad function. This allows data to be transferred from the device
at four times the rate of standard SPI devices.
The Fast Read Quad Output instruction is initiated by executing
an 8-bit command, 6BH, followed by address bits [A₂₃ -A₀] and a
dummy byte. CE must remain active low for the duration of the
Fast Read Dual Output cycle. See Figure 7 for the Fast Read
Quad Output sequence.
CE
MODE3
SCK MODE0
0 12 3 45 67 8
15 16 23 24
31 32 39 40 4142 43 44 45 46 47 48
Dummy
IO0 switches from Input to Ouput
SIO0
6B
MSB
ADD.
MSB
ADD.
A DD.
4 0 4 0 4040 4 0
SIO1
HIGH IMPENANCE
51515151 51
HIGH IMPENANCE
SIO2
62
SIO3
HIGH IMPENANCE
73
N N+1 N+2 N+3 N+4
DOU T DOUT DOUT DOU T DOUT
Note: The input data du ring the dummy clocks is “don’t care”.
However , the IO pins should be high-impefance piror to the fal ling edge o f the first data clock.
Figure 7: Fast Read Quad Output Sequence
Elite Semiconductor Memory Technology Inc.
Publication Date: Jan. 2009
Revision: 0.2
18/42