M53D128168A-2E Datasheet, PDF (2/47 Pages) Elite Semiconductor Memory Technology Inc. – Internal pipelined double-data-rate architecture, two data

ESMT
M53D128168A (2E)
Operation Temperature Condition -40°C~85°C
BALL CONFIGURATION (TOP VIEW)
(BGA60, 8mmX13mmX1.2mm Body, 0.8mm Ball Pitch)
1
2
3
A ^{VSSQ DQ15 VSS}
7
8
9
VDD DQ0 VDDQ
B ^{DQ14 VDDQ DQ13}
DQ2 VSSQ DQ1
C DQ12 VSSQ DQ11
DQ4 VDDQ DQ3
D DQ10 VDDQ DQ9
DQ6 VSSQ DQ5
E DQ8 VSSQ UDQS
LDQS VDDQ DQ7
F NC VSS UDM
LDM VDD NC
G
CLK CLK
WE CAS
H
NC CKE
J
A11 A9
K
A8
A7
L
A6
A5
M
A4
VSS
RAS ^CS
BA1 BA0
A0 A10/AP
A2
A1
VDD
A3
Ball Description
Ball Name
Function
A0~A11,
BA0~BA1
Address inputs
- Row address A0~A11
- Column address A0~ A8
A10/AP : AUTO Precharge
BA0~BA1 : Bank selects (4 Banks)
DQ0~DQ15 Data-in/Data-out
RAS
CAS
WE
V_SS
V_DD
LDQS, UDQS
Row address strobe
Column address strobe
Write enable
Ground
Power
Bi-directional Data Strobe.
LDQS corresponds to the data on DQ0~DQ7;
UDQS correspond to the data on DQ8~DQ15
Ball Name
Function
LDM, UDM
DM is an input mask signal for write data.
LDM corresponds to the data on DQ0~DQ7;
UDM correspond to the data on DQ8~DQ15
CLK, CLK
CKE
CS
V_DDQ
V_SSQ
NC
Clock input
Clock enable
Chip select
Supply Voltage for DQ
Ground for DQ
No connection
Elite Semiconductor Memory Technology Inc.
Publication Date : Jul. 2012
Revision : 1.0
2/47